| Issue |
164186
|
| Summary |
`C.SRLI` RISCV instruction doesn't enforce its `shamt` to be less than 32
|
| Labels |
new issue
|
| Assignees |
|
| Reporter |
moste00
|
The [RISCV spec (page 116)](https://lists.riscv.org/g/tech-unprivileged/attachment/536/0/unpriv-isa-asciidoc.pdf) says `C.SRLI` shift amount must always be non-0, and under the 32-bit arch must be less than 32 (equivaliently, that `shamt[5]` must be 0). The reason being that `shamt[5] == 1` under the 32-bit arch is a custom subspace for third party instructions.
This doesn't appear to be the case with LLVM RISCV target:
<img width="1666" height="157" alt="Image" src="" />
<img width="1666" height="145" alt="Image" src="" />
# Possible Solutions
I first thought of unconditionally setting `shamt[5]` (`Instruction[12]`) to 0, but the spec's wording allows the bit to be non-zero in case of the 64-bit arch, and indeed the [SAIL description](https://github.com/riscv/sail-riscv/blob/1cfc5eda2c14eedfd5cc6eef8f286a090b4b300f/model/extensions/C/zca_insts.sail#L412C3-L412C19) of the RISCV architecture allows the shift amount to exceed 32 if the architecture is 64 bit.
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