| Issue |
173996
|
| Summary |
[X86] Add i512 ADD/SUB expansion on AVX512 targets
|
| Labels |
good first issue,
backend:X86
|
| Assignees |
|
| Reporter |
RKSimon
|
Based off https://www.numberworld.org/y-cruncher/internals/addition.html we can implement i512 ISD::ADD/SUB handling inside X86TargetLowering::ReplaceNodeResults for subtargets that support useAVX512Regs - similar to what we've done for AND/OR/XOR.
The AVX512F variant seems to give a better base implementation than AVX512DQ, we can leave other combines to decide whether to move scalar ops (ADD/SHL) back to mask register ops (KADD/KSHIFT etc.).
We will need to use mayFoldIntoVector to check that its worthwhile to perform this as transferring integer data to the FPU unit can be expensive.
A later patch would be to add support for the carry-in/out handling (ISD::UADDO_CARRY etc.) as well for completely general multi-precision arithmetic - but basic i512 addition/subtraction should be enough for this ticket.
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