| Issue |
179036
|
| Summary |
Provide a target‑independent way to reserve a physical GPR (x86/x86_64 and others)
|
| Labels |
new issue
|
| Assignees |
|
| Reporter |
cpunion
|
Title: Provide a target‑independent way to reserve a physical GPR in LLVM backends (x86/x86_64 and others)
## Motivation
Some frontends need to reserve a specific callee‑saved GPR so the register allocator never uses it (e.g., to hold a per‑thread context pointer).
Currently:
- AArch64/RISC‑V have target features (`+reserve-xN`) or target‑specific options.
- x86 and x86_64 have no supported mechanism to reserve a named GPR.
- `-ffixed-*` is rejected by clang on x86/x86_64, and `+reserve-*` is not a recognized target feature.
- `--reserve-regs-for-regalloc` is implemented only in AArch64.
- Other targets that also appear to lack any reserve‑GPR facility include: ARM (32‑bit), MIPS, PPC, S390x, LoongArch, WASM, AVR, Xtensa (and likely more).
## Request
Add a generic reservation mechanism or x86/x86_64‑specific support so a frontend can reserve a named register without patching the backend.
## Proposed design (either is fine)
1) **Generic LLVM option**
- A common option like `-reserve-regs-for-regalloc=<reg list>` available to all targets, with each backend mapping names → physical regs.
2) **x86/x86_64 target feature**
- Add `+reserve-<reg>` to X86 subtarget (e.g., `+reserve-r12`) and wire it to `getReservedRegs`.
## Implementation sketch (x86/x86_64)
- Parse register names, validate against X86 register info.
- Mark those regs (and aliases) as reserved in `X86RegisterInfo::getReservedRegs`.
- Plumb through clang (`-Xclang -target-feature`) and llc (`-mattr`) as appropriate.
## Benefits
- Enables safe register‑based context passing on x86/x86_64.
- Helps runtimes/JITs/custom ABIs needing a reserved GPR.
- Avoids fragile inline‑asm hacks.
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