| Issue |
181651
|
| Summary |
[DAG] isKnownToBeAPowerOfTwo - improve ISD::SRL handling
|
| Labels |
good first issue,
llvm:SelectionDAG
|
| Assignees |
|
| Reporter |
RKSimon
|
https://github.com/RKSimon/llvm-project/blob/20aff2085c358d3e112b245494161ddb9ffe0410/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp#L4723-L4732
- [ ] The isConstOrConstSplat isSignMask check can be improved by passing in the DemandedElts argument
- [ ] The fallback test should be refactored to check OrZero || isKnownNeverZero first and then call isKnownToBeAPowerOfTwo, with DemandedElts + OrZero arg passthrough
The actual changes are trivial, but this will require test coverage as well - these might be possible by extending existing DAG tests, else maybe add unit tests like we did in https://github.com/llvm/llvm-project/pull/181485
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