Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.120 -> 1.121
PPCInstrInfo.td updated: 1.134 -> 1.135
---
Log message:
Autogen fsel
---
Diffs of the changes: (+6 -14)
PPCISelDAGToDAG.cpp | 12 ------------
PPCInstrInfo.td | 8 ++++++--
2 files changed, 6 insertions(+), 14 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.120
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.121
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.120 Tue Oct 25 15:41:46 2005
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Tue Oct 25 15:55:47 2005
@@ -891,18 +891,6 @@
else
return CurDAG->getTargetNode(PPC::LA, MVT::i32, Tmp, GA);
}
-
- case PPCISD::FSEL: {
- SDOperand Comparison = Select(N->getOperand(0));
- // Extend the comparison to 64-bits.
- if (Comparison.getValueType() == MVT::f32)
- Comparison = CurDAG->getTargetNode(PPC::FMRSD, MVT::f64, Comparison);
-
- unsigned Opc = N->getValueType(0) == MVT::f32 ? PPC::FSELS : PPC::FSELD;
- CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), Comparison,
- Select(N->getOperand(1)), Select(N->getOperand(2)));
- return SDOperand(N, 0);
- }
case ISD::FADD: {
MVT::ValueType Ty = N->getValueType(0);
if (!NoExcessFPPrecision) { // Match FMA ops
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.134
llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.135
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.134 Tue Oct 25 15:41:46 2005
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Tue Oct 25 15:55:47 2005
@@ -22,6 +22,10 @@
def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
+def PPCfsel : SDNode<"PPCISD::FSEL",
+ // Type constraint for fsel.
+ SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
+ SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
//===----------------------------------------------------------------------===//
// PowerPC specific transformation functions and pattern fragments.
@@ -654,11 +658,11 @@
def FSELD : AForm_1<63, 23,
(ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
"fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
- []>;
+ [(set F8RC:$FRT, (PPCfsel
F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
def FSELS : AForm_1<63, 23,
(ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
"fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
- []>;
+ [(set F4RC:$FRT, (PPCfsel
F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
def FADD : AForm_2<63, 21,
(ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
"fadd $FRT, $FRA, $FRB", FPGeneral,
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