Changes in directory llvm/lib/Target/SparcV8:
SparcV8ISelDAGToDAG.cpp added (r1.1)
Makefile updated: 1.11 -> 1.12
SparcV8.h updated: 1.6 -> 1.7
SparcV8TargetMachine.cpp updated: 1.32 -> 1.33
---
Log message:
Add the framework for a dag-dag isel
---
Diffs of the changes: (+185 -2)
Makefile | 3
SparcV8.h | 2
SparcV8ISelDAGToDAG.cpp | 172 +++++++++++++++++++++++++++++++++++++++++++++++
SparcV8TargetMachine.cpp | 10 ++
4 files changed, 185 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
diff -c /dev/null llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp:1.1
*** /dev/null Sat Dec 17 01:47:11 2005
--- llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp Sat Dec 17 01:47:01 2005
***************
*** 0 ****
--- 1,172 ----
+ //===-- SparcV8ISelDAGToDAG.cpp - A dag to dag inst selector for SparcV8
--===//
+ //
+ // The LLVM Compiler Infrastructure
+ //
+ // This file was developed by Chris Lattner and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for
details.
+ //
+
//===----------------------------------------------------------------------===//
+ //
+ // This file defines an instruction selector for the V8 target
+ //
+
//===----------------------------------------------------------------------===//
+
+ #include "SparcV8.h"
+ #include "SparcV8TargetMachine.h"
+ #include "llvm/CodeGen/SelectionDAG.h"
+ #include "llvm/CodeGen/SelectionDAGISel.h"
+ #include "llvm/Target/TargetLowering.h"
+ #include "llvm/Support/Debug.h"
+ #include <iostream>
+ using namespace llvm;
+
+
//===----------------------------------------------------------------------===//
+ // TargetLowering Implementation
+
//===----------------------------------------------------------------------===//
+
+ namespace {
+ class SparcV8TargetLowering : public TargetLowering {
+ public:
+ SparcV8TargetLowering(TargetMachine &TM);
+
+ virtual std::vector<SDOperand>
+ LowerArguments(Function &F, SelectionDAG &DAG);
+ virtual std::pair<SDOperand, SDOperand>
+ LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
+ unsigned CC,
+ bool isTailCall, SDOperand Callee, ArgListTy &Args,
+ SelectionDAG &DAG);
+
+ virtual SDOperand LowerReturnTo(SDOperand Chain, SDOperand Op,
+ SelectionDAG &DAG);
+ virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP,
+ Value *VAListV, SelectionDAG &DAG);
+ virtual std::pair<SDOperand,SDOperand>
+ LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
+ const Type *ArgTy, SelectionDAG &DAG);
+ virtual std::pair<SDOperand, SDOperand>
+ LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned
Depth,
+ SelectionDAG &DAG);
+ };
+ }
+
+ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
+ : TargetLowering(TM) {
+
+ // Set up the register classes.
+ addRegisterClass(MVT::i32, V8::IntRegsRegisterClass);
+ addRegisterClass(MVT::f32, V8::FPRegsRegisterClass);
+ addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass);
+
+ computeRegisterProperties();
+ }
+
+ std::vector<SDOperand>
+ SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
+ assert(0 && "Unimp");
+ abort();
+ }
+
+ std::pair<SDOperand, SDOperand>
+ SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
+ bool isVarArg, unsigned CC,
+ bool isTailCall, SDOperand Callee,
+ ArgListTy &Args, SelectionDAG &DAG) {
+ assert(0 && "Unimp");
+ abort();
+ }
+
+ SDOperand SparcV8TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
+ SelectionDAG &DAG) {
+ assert(0 && "Unimp");
+ abort();
+ }
+
+ SDOperand SparcV8TargetLowering::LowerVAStart(SDOperand Chain, SDOperand
VAListP,
+ Value *VAListV, SelectionDAG
&DAG) {
+ assert(0 && "Unimp");
+ abort();
+ }
+
+ std::pair<SDOperand,SDOperand>
+ SparcV8TargetLowering::LowerVAArg(SDOperand Chain, SDOperand VAListP, Value
*VAListV,
+ const Type *ArgTy, SelectionDAG &DAG) {
+ assert(0 && "Unimp");
+ abort();
+ }
+
+ std::pair<SDOperand, SDOperand>
+ SparcV8TargetLowering::LowerFrameReturnAddress(bool isFrameAddr, SDOperand
Chain, unsigned Depth,
+ SelectionDAG &DAG) {
+ assert(0 && "Unimp");
+ abort();
+ }
+
+
//===----------------------------------------------------------------------===//
+ // Instruction Selector Implementation
+
//===----------------------------------------------------------------------===//
+
+ //===--------------------------------------------------------------------===//
+ /// SparcV8DAGToDAGISel - PPC specific code to select Sparc V8 machine
+ /// instructions for SelectionDAG operations.
+ ///
+ namespace {
+ class SparcV8DAGToDAGISel : public SelectionDAGISel {
+ SparcV8TargetLowering V8Lowering;
+ public:
+ SparcV8DAGToDAGISel(TargetMachine &TM)
+ : SelectionDAGISel(V8Lowering), V8Lowering(TM) {}
+
+ SDOperand Select(SDOperand Op);
+
+ /// InstructionSelectBasicBlock - This callback is invoked by
+ /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
+ virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
+
+ virtual const char *getPassName() const {
+ return "PowerPC DAG->DAG Pattern Instruction Selection";
+ }
+
+ // Include the pieces autogenerated from the target description.
+ #include "SparcV8GenDAGISel.inc"
+ };
+ } // end anonymous namespace
+
+ /// InstructionSelectBasicBlock - This callback is invoked by
+ /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
+ void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
+ DEBUG(BB->dump());
+
+ // Select target instructions for the DAG.
+ DAG.setRoot(Select(DAG.getRoot()));
+ CodeGenMap.clear();
+ DAG.RemoveDeadNodes();
+
+ // Emit machine code to BB.
+ ScheduleAndEmitDAG(DAG);
+ }
+
+
+ SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
+ SDNode *N = Op.Val;
+ if (N->getOpcode() >= ISD::BUILTIN_OP_END/* &&
+ N->getOpcode() < V8ISD::FIRST_NUMBER*/)
+ return Op; // Already selected.
+ // If this has already been converted, use it.
+ std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
+ if (CGMI != CodeGenMap.end()) return CGMI->second;
+
+ switch (N->getOpcode()) {
+ default: break;
+ }
+
+ return SelectCode(Op);
+ }
+
+
+ /// createPPCISelDag - This pass converts a legalized DAG into a
+ /// PowerPC-specific DAG, ready for instruction scheduling.
+ ///
+ FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) {
+ return new SparcV8DAGToDAGISel(TM);
+ }
Index: llvm/lib/Target/SparcV8/Makefile
diff -u llvm/lib/Target/SparcV8/Makefile:1.11
llvm/lib/Target/SparcV8/Makefile:1.12
--- llvm/lib/Target/SparcV8/Makefile:1.11 Fri Dec 16 00:34:17 2005
+++ llvm/lib/Target/SparcV8/Makefile Sat Dec 17 01:47:01 2005
@@ -13,7 +13,8 @@
# Make sure that tblgen is run, first thing.
BUILT_SOURCES = SparcV8GenRegisterInfo.h.inc SparcV8GenRegisterNames.inc \
SparcV8GenRegisterInfo.inc SparcV8GenInstrNames.inc \
- SparcV8GenInstrInfo.inc SparcV8GenAsmWriter.inc
+ SparcV8GenInstrInfo.inc SparcV8GenAsmWriter.inc \
+ SparcV8GenDAGISel.inc
include $(LEVEL)/Makefile.common
Index: llvm/lib/Target/SparcV8/SparcV8.h
diff -u llvm/lib/Target/SparcV8/SparcV8.h:1.6
llvm/lib/Target/SparcV8/SparcV8.h:1.7
--- llvm/lib/Target/SparcV8/SparcV8.h:1.6 Thu Apr 21 18:21:30 2005
+++ llvm/lib/Target/SparcV8/SparcV8.h Sat Dec 17 01:47:01 2005
@@ -23,6 +23,8 @@
class TargetMachine;
FunctionPass *createSparcV8SimpleInstructionSelector(TargetMachine &TM);
+ FunctionPass *createSparcV8ISelDag(TargetMachine &TM);
+
FunctionPass *createSparcV8CodePrinterPass(std::ostream &OS,
TargetMachine &TM);
FunctionPass *createSparcV8DelaySlotFillerPass(TargetMachine &TM);
Index: llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp
diff -u llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp:1.32
llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp:1.33
--- llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp:1.32 Fri Dec 16
00:06:07 2005
+++ llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp Sat Dec 17 01:47:01 2005
@@ -20,12 +20,17 @@
#include "llvm/Target/TargetOptions.h"
#include "llvm/Target/TargetMachineRegistry.h"
#include "llvm/Transforms/Scalar.h"
+#include "llvm/Support/CommandLine.h"
#include <iostream>
using namespace llvm;
namespace {
// Register the target.
RegisterTarget<SparcV8TargetMachine> X("sparcv8"," SPARC V8
(experimental)");
+
+ cl::opt<bool> DisableV8DAGDAG("disable-v8-dag-isel", cl::Hidden,
+ cl::desc("Disable DAG-to-DAG isel for V8"),
+ cl::init(1));
}
/// SparcV8TargetMachine ctor - Create an ILP32 architecture model
@@ -87,7 +92,10 @@
if (PrintMachineCode)
PM.add(new PrintFunctionPass());
- PM.add(createSparcV8SimpleInstructionSelector(*this));
+ if (DisableV8DAGDAG)
+ PM.add(createSparcV8SimpleInstructionSelector(*this));
+ else
+ PM.add(createSparcV8ISelDag(*this));
// Print machine instructions as they were initially generated.
if (PrintMachineCode)
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