Changes in directory llvm/lib/Target/IA64:
IA64InstrInfo.td updated: 1.38 -> 1.39
IA64RegisterInfo.cpp updated: 1.9 -> 1.10
IA64RegisterInfo.td updated: 1.12 -> 1.13
---
Log message:
use proper (82-bit) spills/fills when spilling FP regs, so that
divides don't get broken. this fixes obsequi, smg2000, and probably
a bunch of other stuff (tm)
---
Diffs of the changes: (+11 -3)
IA64InstrInfo.td | 4 ++++
IA64RegisterInfo.cpp | 4 ++--
IA64RegisterInfo.td | 6 +++++-
3 files changed, 11 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/IA64/IA64InstrInfo.td
diff -u llvm/lib/Target/IA64/IA64InstrInfo.td:1.38
llvm/lib/Target/IA64/IA64InstrInfo.td:1.39
--- llvm/lib/Target/IA64/IA64InstrInfo.td:1.38 Mon Jan 16 00:33:38 2006
+++ llvm/lib/Target/IA64/IA64InstrInfo.td Mon Jan 16 20:04:52 2006
@@ -537,6 +537,8 @@
"stfs [$dstPtr] = $value;;">;
def STF8 : AForm<0x03, 0x0b, (ops GR:$dstPtr, FP:$value),
"stfd [$dstPtr] = $value;;">;
+ def STF_SPILL : AForm<0x03, 0x0b, (ops GR:$dstPtr, FP:$value),
+ "stf.spill [$dstPtr] = $value;;">;
}
let isLoad = 1 in {
@@ -552,6 +554,8 @@
"ldfs $dst = [$srcPtr];;">;
def LDF8 : AForm<0x03, 0x0b, (ops FP:$dst, GR:$srcPtr),
"ldfd $dst = [$srcPtr];;">;
+ def LDF_FILL : AForm<0x03, 0x0b, (ops FP:$dst, GR:$srcPtr),
+ "ldf.fill $dst = [$srcPtr];;">;
}
def POPCNT : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src),
Index: llvm/lib/Target/IA64/IA64RegisterInfo.cpp
diff -u llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.9
llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.10
--- llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.9 Thu Oct 27 23:58:24 2005
+++ llvm/lib/Target/IA64/IA64RegisterInfo.cpp Mon Jan 16 20:04:52 2006
@@ -40,7 +40,7 @@
const TargetRegisterClass *RC)
const{
if (RC == IA64::FPRegisterClass) {
- BuildMI(MBB, MI, IA64::STF8, 2).addFrameIndex(FrameIdx).addReg(SrcReg);
+ BuildMI(MBB, MI, IA64::STF_SPILL,
2).addFrameIndex(FrameIdx).addReg(SrcReg);
} else if (RC == IA64::GRRegisterClass) {
BuildMI(MBB, MI, IA64::ST8, 2).addFrameIndex(FrameIdx).addReg(SrcReg);
}
@@ -63,7 +63,7 @@
const TargetRegisterClass
*RC)const{
if (RC == IA64::FPRegisterClass) {
- BuildMI(MBB, MI, IA64::LDF8, 1, DestReg).addFrameIndex(FrameIdx);
+ BuildMI(MBB, MI, IA64::LDF_FILL, 1, DestReg).addFrameIndex(FrameIdx);
} else if (RC == IA64::GRRegisterClass) {
BuildMI(MBB, MI, IA64::LD8, 1, DestReg).addFrameIndex(FrameIdx);
} else if (RC == IA64::PRRegisterClass) {
Index: llvm/lib/Target/IA64/IA64RegisterInfo.td
diff -u llvm/lib/Target/IA64/IA64RegisterInfo.td:1.12
llvm/lib/Target/IA64/IA64RegisterInfo.td:1.13
--- llvm/lib/Target/IA64/IA64RegisterInfo.td:1.12 Wed Dec 21 21:56:03 2005
+++ llvm/lib/Target/IA64/IA64RegisterInfo.td Mon Jan 16 20:04:52 2006
@@ -282,7 +282,11 @@
// these are the scratch (+stacked) FP registers
-def FP : RegisterClass<"IA64", [f64], 64,
+
+// the 128 here is to make stf.spill/ldf.fill happy,
+// when storing full (82-bit) FP regs to stack slots
+// we need to 16-byte align
+def FP : RegisterClass<"IA64", [f64], 128,
[F6, F7,
F8, F9, F10, F11, F12, F13, F14, F15,
F32, F33, F34, F35, F36, F37, F38, F39,
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