Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.91 -> 1.92 --- Log message: add two dag combines: (C1-X) == C2 --> X == C1-C2 (X+C1) == C2 --> X == C2-C1 This allows us to compile this: bool %X(int %X) { %Y = add int %X, 14 %Z = setne int %Y, 12345 ret bool %Z } into this: _X: cmpl $12331, 4(%esp) setne %al movzbl %al, %eax andl $1, %eax ret not this: _X: movl $14, %eax addl 4(%esp), %eax cmpl $12345, %eax setne %al movzbl %al, %eax andl $1, %eax ret Testcase here: Regression/CodeGen/X86/compare-add.ll nukage of the and coming up next. --- Diffs of the changes: (+25 -8) DAGCombiner.cpp | 33 +++++++++++++++++++++++++-------- 1 files changed, 25 insertions(+), 8 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.91 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.92 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.91 Wed Feb 1 01:19:44 2006 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Feb 2 00:36:13 2006 @@ -2623,19 +2623,36 @@ return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond); } } - - // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. Common for condcodes. - if (N0.getOpcode() == ISD::XOR) - if (ConstantSDNode *XORC = dyn_cast<ConstantSDNode>(N0.getOperand(1))) - if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { + + if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { + if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { + // Turn (X+C1) == C2 --> X == C2-C1 + if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) { + return DAG.getSetCC(VT, N0.getOperand(0), + DAG.getConstant(RHSC->getValue()-LHSR->getValue(), + N0.getValueType()), Cond); + } + + // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. + if (N0.getOpcode() == ISD::XOR) // If we know that all of the inverted bits are zero, don't bother // performing the inversion. - if (TLI.MaskedValueIsZero(N0.getOperand(0), ~XORC->getValue())) + if (TLI.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue())) return DAG.getSetCC(VT, N0.getOperand(0), - DAG.getConstant(XORC->getValue()^RHSC->getValue(), + DAG.getConstant(LHSR->getValue()^RHSC->getValue(), N0.getValueType()), Cond); + } + + // Turn (C1-X) == C2 --> X == C1-C2 + if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { + if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) { + return DAG.getSetCC(VT, N0.getOperand(1), + DAG.getConstant(SUBC->getValue()-RHSC->getValue(), + N0.getValueType()), Cond); } - + } + } + // Simplify (X+Z) == X --> Z == 0 if (N0.getOperand(0) == N1) return DAG.getSetCC(VT, N0.getOperand(1), _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits