Changes in directory llvm/lib/Target/Sparc:
SparcInstrInfo.td updated: 1.118 -> 1.119 SparcTargetMachine.cpp updated: 1.40 -> 1.41 --- Log message: add an option to turn on LSR. --- Diffs of the changes: (+62 -1) SparcInstrInfo.td | 56 +++++++++++++++++++++++++++++++++++++++++++++++++ SparcTargetMachine.cpp | 7 +++++- 2 files changed, 62 insertions(+), 1 deletion(-) Index: llvm/lib/Target/Sparc/SparcInstrInfo.td diff -u llvm/lib/Target/Sparc/SparcInstrInfo.td:1.118 llvm/lib/Target/Sparc/SparcInstrInfo.td:1.119 --- llvm/lib/Target/Sparc/SparcInstrInfo.td:1.118 Sat Feb 4 23:50:24 2006 +++ llvm/lib/Target/Sparc/SparcInstrInfo.td Wed Feb 8 23:06:36 2006 @@ -493,6 +493,7 @@ def UMULri : F3_2<2, 0b001010, (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), "umul $b, $c, $dst", []>; + def SMULrr : F3_1<2, 0b001011, (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), "smul $b, $c, $dst", @@ -502,6 +503,61 @@ "smul $b, $c, $dst", [(set IntRegs:$dst, (mul IntRegs:$b, simm13:$c))]>; +/* +//===------------------------- +// Sparc Example +defm intinst<id OPC1, id OPC2, bits Opc, string asmstr, SDNode code> { + def OPC1 : F3_1<2, Opc, asmstr, (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), + [(set IntRegs:$dst, (code IntRegs:$b, IntRegs:$c))]>; + def OPC2 : F3_2<2, Opc, asmstr, (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), + [(set IntRegs:$dst, (code IntRegs:$b, simm13:$c))]>; +} +defm intinst_np<id OPC1, id OPC2, bits Opc, string asmstr> { + def OPC1 : F3_1<2, Opc, asmstr, (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), + []>; + def OPC2 : F3_2<2, Opc, asmstr, (ops IntRegs:$dst, IntRegs:$b, i32imm:$c), + []>; +} + +def intinstnp< ADDXrr, ADDXri, 0b001000, "addx $b, $c, $dst">; +def intinst < SUBrr, SUBri, 0b000100, "sub $b, $c, $dst", sub>; +def intinstnp< SUBXrr, SUBXri, 0b001100, "subx $b, $c, $dst">; +def intinst <SUBCCrr, SUBCCri, 0b010100, "subcc $b, $c, $dst", SPcmpicc>; +def intinst < SMULrr, SMULri, 0b001011, "smul $b, $c, $dst", mul>; + +//===------------------------- +// X86 Example +defm cmov32<id OPC1, id OPC2, int opc, string asmstr, PatLeaf cond> { + def OPC1 : I<opc, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2), + asmstr+" {$src2, $dst|$dst, $src2}", + [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, cond))]>, TB; + def OPC2 : I<opc, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), + asmstr+" {$src2, $dst|$dst, $src2}", + [(set R32:$dst, (X86cmov R32:$src1, + (loadi32 addr:$src2), cond))]>, TB; +} + +def cmov<CMOVL32rr, CMOVL32rm, 0x4C, "cmovl", X86_COND_L>; +def cmov<CMOVB32rr, CMOVB32rm, 0x4C, "cmovb", X86_COND_B>; + +//===------------------------- +// PPC Example + +def fpunop<id OPC1, id OPC2, id FORM, int op1, int op2, int op3, string asmstr, + SDNode code> { + def OPC1 : FORM<op1, op3, (ops F4RC:$frD, F4RC:$frB), + asmstr+" $frD, $frB", FPGeneral, + [(set F4RC:$frD, (code F4RC:$frB))]>; + def OPC2 : FORM<op2, op3, (ops F8RC:$frD, F8RC:$frB), + asmstr+" $frD, $frB", FPGeneral, + [(set F8RC:$frD, (code F8RC:$frB))]>; +} + +def fpunop< FABSS, FABSD, XForm_26, 63, 63, 264, "fabs", fabs>; +def fpunop<FNABSS, FNABSD, XForm_26, 63, 63, 136, "fnabs", fnabs>; +def fpunop< FNEGS, FNEGD, XForm_26, 63, 63, 40, "fneg", fneg>; +*/ + // Section B.19 - Divide Instructions, p. 115 def UDIVrr : F3_1<2, 0b001110, (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), Index: llvm/lib/Target/Sparc/SparcTargetMachine.cpp diff -u llvm/lib/Target/Sparc/SparcTargetMachine.cpp:1.40 llvm/lib/Target/Sparc/SparcTargetMachine.cpp:1.41 --- llvm/lib/Target/Sparc/SparcTargetMachine.cpp:1.40 Sat Feb 4 23:50:24 2006 +++ llvm/lib/Target/Sparc/SparcTargetMachine.cpp Wed Feb 8 23:06:36 2006 @@ -27,6 +27,8 @@ namespace { // Register the target. RegisterTarget<SparcTargetMachine> X("sparc", " SPARC"); + + cl::opt<bool> EnableLSR("enable-sparc-lsr", cl::Hidden); } /// SparcTargetMachine ctor - Create an ILP32 architecture model @@ -65,6 +67,9 @@ bool Fast) { if (FileType != TargetMachine::AssemblyFile) return true; + // Run loop strength reduction before anything else. + if (EnableLSR && !Fast) PM.add(createLoopStrengthReducePass()); + // FIXME: Implement efficient support for garbage collection intrinsics. PM.add(createLowerGCPass()); @@ -73,7 +78,7 @@ // FIXME: implement the switch instruction in the instruction selector. PM.add(createLowerSwitchPass()); - + // Print LLVM code input to instruction selector: if (PrintMachineCode) PM.add(new PrintFunctionPass()); _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits