Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.126 -> 1.127 LegalizeDAG.cpp updated: 1.315 -> 1.316 SelectionDAG.cpp updated: 1.270 -> 1.271 SelectionDAGISel.cpp updated: 1.192 -> 1.193 --- Log message: Remove BRTWOWAY* Make the PPC backend not dependent on BRTWOWAY_CC and make the branch selector smarter about the code it generates, fixing a case in the readme. --- Diffs of the changes: (+5 -181) DAGCombiner.cpp | 68 ------------------------------------ LegalizeDAG.cpp | 94 --------------------------------------------------- SelectionDAG.cpp | 16 -------- SelectionDAGISel.cpp | 8 ++-- 4 files changed, 5 insertions(+), 181 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.126 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.127 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.126 Mon Mar 13 12:37:30 2006 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Mar 16 19:40:33 2006 @@ -206,9 +206,7 @@ SDOperand visitFNEG(SDNode *N); SDOperand visitFABS(SDNode *N); SDOperand visitBRCOND(SDNode *N); - SDOperand visitBRCONDTWOWAY(SDNode *N); SDOperand visitBR_CC(SDNode *N); - SDOperand visitBRTWOWAY_CC(SDNode *N); SDOperand visitLOAD(SDNode *N); SDOperand visitSTORE(SDNode *N); @@ -639,9 +637,7 @@ case ISD::FNEG: return visitFNEG(N); case ISD::FABS: return visitFABS(N); case ISD::BRCOND: return visitBRCOND(N); - case ISD::BRCONDTWOWAY: return visitBRCONDTWOWAY(N); case ISD::BR_CC: return visitBR_CC(N); - case ISD::BRTWOWAY_CC: return visitBRTWOWAY_CC(N); case ISD::LOAD: return visitLOAD(N); case ISD::STORE: return visitSTORE(N); } @@ -2219,35 +2215,6 @@ return SDOperand(); } -SDOperand DAGCombiner::visitBRCONDTWOWAY(SDNode *N) { - SDOperand Chain = N->getOperand(0); - SDOperand N1 = N->getOperand(1); - SDOperand N2 = N->getOperand(2); - SDOperand N3 = N->getOperand(3); - ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); - - // unconditional branch to true mbb - if (N1C && N1C->getValue() == 1) - return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); - // unconditional branch to false mbb - if (N1C && N1C->isNullValue()) - return DAG.getNode(ISD::BR, MVT::Other, Chain, N3); - // fold a brcondtwoway with a setcc condition into a BRTWOWAY_CC node if - // BRTWOWAY_CC is legal on the target. - if (N1.getOpcode() == ISD::SETCC && - TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) { - std::vector<SDOperand> Ops; - Ops.push_back(Chain); - Ops.push_back(N1.getOperand(2)); - Ops.push_back(N1.getOperand(0)); - Ops.push_back(N1.getOperand(1)); - Ops.push_back(N2); - Ops.push_back(N3); - return DAG.getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops); - } - return SDOperand(); -} - // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. // SDOperand DAGCombiner::visitBR_CC(SDNode *N) { @@ -2273,41 +2240,6 @@ return SDOperand(); } -SDOperand DAGCombiner::visitBRTWOWAY_CC(SDNode *N) { - SDOperand Chain = N->getOperand(0); - SDOperand CCN = N->getOperand(1); - SDOperand LHS = N->getOperand(2); - SDOperand RHS = N->getOperand(3); - SDOperand N4 = N->getOperand(4); - SDOperand N5 = N->getOperand(5); - - SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), LHS, RHS, - cast<CondCodeSDNode>(CCN)->get(), false); - ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); - - // fold select_cc lhs, rhs, x, x, cc -> x - if (N4 == N5) - return DAG.getNode(ISD::BR, MVT::Other, Chain, N4); - // fold select_cc true, x, y -> x - if (SCCC && SCCC->getValue()) - return DAG.getNode(ISD::BR, MVT::Other, Chain, N4); - // fold select_cc false, x, y -> y - if (SCCC && SCCC->isNullValue()) - return DAG.getNode(ISD::BR, MVT::Other, Chain, N5); - // fold to a simpler setcc - if (SCC.Val && SCC.getOpcode() == ISD::SETCC) { - std::vector<SDOperand> Ops; - Ops.push_back(Chain); - Ops.push_back(SCC.getOperand(2)); - Ops.push_back(SCC.getOperand(0)); - Ops.push_back(SCC.getOperand(1)); - Ops.push_back(N4); - Ops.push_back(N5); - return DAG.getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops); - } - return SDOperand(); -} - SDOperand DAGCombiner::visitLOAD(SDNode *N) { SDOperand Chain = N->getOperand(0); SDOperand Ptr = N->getOperand(1); Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.315 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.316 --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.315 Wed Mar 15 16:19:18 2006 +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Mar 16 19:40:33 2006 @@ -945,100 +945,6 @@ break; } break; - case ISD::BRCONDTWOWAY: - Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. - switch (getTypeAction(Node->getOperand(1).getValueType())) { - case Expand: assert(0 && "It's impossible to expand bools"); - case Legal: - Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. - break; - case Promote: - Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. - break; - } - - // If this target does not support BRCONDTWOWAY, lower it to a BRCOND/BR - // pair. - switch (TLI.getOperationAction(ISD::BRCONDTWOWAY, MVT::Other)) { - case TargetLowering::Promote: - default: assert(0 && "This action is not supported yet!"); - case TargetLowering::Legal: - Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2), - Node->getOperand(3)); - break; - case TargetLowering::Expand: - // If BRTWOWAY_CC is legal for this target, then simply expand this node - // to that. Otherwise, skip BRTWOWAY_CC and expand directly to a - // BRCOND/BR pair. - if (TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) { - if (Tmp2.getOpcode() == ISD::SETCC) { - Tmp3 = Tmp2.getOperand(0); - Tmp4 = Tmp2.getOperand(1); - Tmp2 = Tmp2.getOperand(2); - } else { - Tmp3 = Tmp2; - Tmp4 = DAG.getConstant(0, Tmp2.getValueType()); - Tmp2 = DAG.getCondCode(ISD::SETNE); - } - std::vector<SDOperand> Ops; - Ops.push_back(Tmp1); - Ops.push_back(Tmp2); - Ops.push_back(Tmp3); - Ops.push_back(Tmp4); - Ops.push_back(Node->getOperand(2)); - Ops.push_back(Node->getOperand(3)); - Result = DAG.getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops); - } else { - Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, - Node->getOperand(2)); - Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(3)); - } - break; - } - break; - case ISD::BRTWOWAY_CC: { - Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. - // Ensure that libcalls are emitted before a branch. - Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); - Tmp1 = LegalizeOp(Tmp1); - LastCALLSEQ_END = DAG.getEntryNode(); - - Tmp2 = Node->getOperand(2); // LHS - Tmp3 = Node->getOperand(3); // RHS - Tmp4 = Node->getOperand(1); // CC - - LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4); - - // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, - // the LHS is a legal SETCC itself. In this case, we need to compare - // the result against zero to select between true and false values. - if (Tmp3.Val == 0) { - Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); - Tmp4 = DAG.getCondCode(ISD::SETNE); - } - std::vector<SDOperand> Ops; - Ops.push_back(Tmp1); - Ops.push_back(Tmp4); - Ops.push_back(Tmp2); - Ops.push_back(Tmp3); - Ops.push_back(Node->getOperand(4)); - Ops.push_back(Node->getOperand(5)); - Result = DAG.UpdateNodeOperands(Result, Ops); - - // Everything is legal, see if we should expand this op or something. - switch (TLI.getOperationAction(ISD::BRTWOWAY_CC, MVT::Other)) { - default: assert(0 && "This action is not supported yet!"); - case TargetLowering::Legal: break; - case TargetLowering::Expand: - Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, - DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp2, - Tmp3, Tmp4), - Result.getOperand(4)); - Result = DAG.getNode(ISD::BR, MVT::Other, Result, Result.getOperand(5)); - break; - } - break; - } case ISD::LOAD: { Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.270 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.271 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.270 Wed Mar 15 16:19:46 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Mar 16 19:40:33 2006 @@ -1486,18 +1486,6 @@ ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Ops[1].Val); switch (Opcode) { default: break; - case ISD::BRCONDTWOWAY: - if (N1C) - if (N1C->getValue()) // Unconditional branch to true dest. - return getNode(ISD::BR, MVT::Other, Ops[0], Ops[2]); - else // Unconditional branch to false dest. - return getNode(ISD::BR, MVT::Other, Ops[0], Ops[3]); - break; - case ISD::BRTWOWAY_CC: - assert(Ops.size() == 6 && "BRTWOWAY_CC takes 6 operands!"); - assert(Ops[2].getValueType() == Ops[3].getValueType() && - "LHS and RHS of comparison must have same type!"); - break; case ISD::TRUNCSTORE: { assert(Ops.size() == 5 && "TRUNCSTORE takes 5 operands!"); MVT::ValueType EVT = cast<VTSDNode>(Ops[4])->getVT(); @@ -2692,9 +2680,7 @@ // Control flow instructions case ISD::BR: return "br"; case ISD::BRCOND: return "brcond"; - case ISD::BRCONDTWOWAY: return "brcondtwoway"; - case ISD::BR_CC: return "br_cc"; - case ISD::BRTWOWAY_CC: return "brtwoway_cc"; + case ISD::BR_CC: return "br_cc"; case ISD::RET: return "ret"; case ISD::CALLSEQ_START: return "callseq_start"; case ISD::CALLSEQ_END: return "callseq_end"; Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.192 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.193 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.192 Thu Mar 16 17:05:19 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Mar 16 19:40:33 2006 @@ -691,10 +691,10 @@ SDOperand True = DAG.getConstant(1, Cond.getValueType()); Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True); } - Ops.push_back(Cond); - Ops.push_back(DAG.getBasicBlock(Succ0MBB)); - Ops.push_back(DAG.getBasicBlock(Succ1MBB)); - DAG.setRoot(DAG.getNode(ISD::BRCONDTWOWAY, MVT::Other, Ops)); + SDOperand True = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond, + DAG.getBasicBlock(Succ0MBB)); + DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, True, + DAG.getBasicBlock(Succ1MBB))); } } } _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits