Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.109 -> 1.110 --- Log message: Disable the i32->float G5 optimization. It is unsafe, as documented in the comment. This fixes 177.mesa, and McCat/09-vor with the td scheduler. --- Diffs of the changes: (+7 -1) PPCISelLowering.cpp | 8 +++++++- 1 files changed, 7 insertions(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.109 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.110 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.109 Fri Mar 24 01:48:08 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Fri Mar 24 01:53:47 2006 @@ -140,7 +140,12 @@ // They also have instructions for converting between i64 and fp. setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); - setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); + + // FIXME: disable this lowered code. This generates 64-bit register values, + // and we don't model the fact that the top part is clobbered by calls. We + // need to flag these together so that the value isn't live across a call. + //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); + // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote); } else { @@ -359,6 +364,7 @@ FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP); return FP; } + break; case ISD::SELECT_CC: { // Turn FP only select_cc's into fsel instructions. _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits