Changes in directory llvm/lib/Target/Sparc:
SparcRegisterInfo.td updated: 1.29 -> 1.30 --- Log message: Add dwarf register numbering to register data. --- Diffs of the changes: (+80 -31) SparcRegisterInfo.td | 111 ++++++++++++++++++++++++++++++++++++--------------- 1 files changed, 80 insertions(+), 31 deletions(-) Index: llvm/lib/Target/Sparc/SparcRegisterInfo.td diff -u llvm/lib/Target/Sparc/SparcRegisterInfo.td:1.29 llvm/lib/Target/Sparc/SparcRegisterInfo.td:1.30 --- llvm/lib/Target/Sparc/SparcRegisterInfo.td:1.29 Fri Feb 10 00:58:25 2006 +++ llvm/lib/Target/Sparc/SparcRegisterInfo.td Fri Mar 24 15:15:58 2006 @@ -32,41 +32,90 @@ } // Integer registers -def G0 : Ri< 0, "G0">; def G1 : Ri< 1, "G1">; def G2 : Ri< 2, "G2">; -def G3 : Ri< 3, "G3">; def G4 : Ri< 4, "G4">; def G5 : Ri< 5, "G5">; -def G6 : Ri< 6, "G6">; def G7 : Ri< 7, "G7">; -def O0 : Ri< 8, "O0">; def O1 : Ri< 9, "O1">; def O2 : Ri<10, "O2">; -def O3 : Ri<11, "O3">; def O4 : Ri<12, "O4">; def O5 : Ri<13, "O5">; -def O6 : Ri<14, "O6">; def O7 : Ri<15, "O7">; -def L0 : Ri<16, "L0">; def L1 : Ri<17, "L1">; def L2 : Ri<18, "L2">; -def L3 : Ri<19, "L3">; def L4 : Ri<20, "L4">; def L5 : Ri<21, "L5">; -def L6 : Ri<22, "L6">; def L7 : Ri<23, "L7">; -def I0 : Ri<24, "I0">; def I1 : Ri<25, "I1">; def I2 : Ri<26, "I2">; -def I3 : Ri<27, "I3">; def I4 : Ri<28, "I4">; def I5 : Ri<29, "I5">; -def I6 : Ri<30, "I6">; def I7 : Ri<31, "I7">; +def G0 : Ri< 0, "G0">, DwarfRegNum<0>; +def G1 : Ri< 1, "G1">, DwarfRegNum<1>; +def G2 : Ri< 2, "G2">, DwarfRegNum<2>; +def G3 : Ri< 3, "G3">, DwarfRegNum<3>; +def G4 : Ri< 4, "G4">, DwarfRegNum<4>; +def G5 : Ri< 5, "G5">, DwarfRegNum<5>; +def G6 : Ri< 6, "G6">, DwarfRegNum<6>; +def G7 : Ri< 7, "G7">, DwarfRegNum<7>; +def O0 : Ri< 8, "O0">, DwarfRegNum<8>; +def O1 : Ri< 9, "O1">, DwarfRegNum<9>; +def O2 : Ri<10, "O2">, DwarfRegNum<10>; +def O3 : Ri<11, "O3">, DwarfRegNum<11>; +def O4 : Ri<12, "O4">, DwarfRegNum<12>; +def O5 : Ri<13, "O5">, DwarfRegNum<13>; +def O6 : Ri<14, "O6">, DwarfRegNum<14>; +def O7 : Ri<15, "O7">, DwarfRegNum<15>; +def L0 : Ri<16, "L0">, DwarfRegNum<16>; +def L1 : Ri<17, "L1">, DwarfRegNum<17>; +def L2 : Ri<18, "L2">, DwarfRegNum<18>; +def L3 : Ri<19, "L3">, DwarfRegNum<19>; +def L4 : Ri<20, "L4">, DwarfRegNum<20>; +def L5 : Ri<21, "L5">, DwarfRegNum<21>; +def L6 : Ri<22, "L6">, DwarfRegNum<22>; +def L7 : Ri<23, "L7">, DwarfRegNum<23>; +def I0 : Ri<24, "I0">, DwarfRegNum<24>; +def I1 : Ri<25, "I1">, DwarfRegNum<25>; +def I2 : Ri<26, "I2">, DwarfRegNum<26>; +def I3 : Ri<27, "I3">, DwarfRegNum<27>; +def I4 : Ri<28, "I4">, DwarfRegNum<28>; +def I5 : Ri<29, "I5">, DwarfRegNum<29>; +def I6 : Ri<30, "I6">, DwarfRegNum<30>; +def I7 : Ri<31, "I7">, DwarfRegNum<31>; // Floating-point registers -def F0 : Rf< 0, "F0">; def F1 : Rf< 1, "F1">; def F2 : Rf< 2, "F2">; -def F3 : Rf< 3, "F3">; def F4 : Rf< 4, "F4">; def F5 : Rf< 5, "F5">; -def F6 : Rf< 6, "F6">; def F7 : Rf< 7, "F7">; def F8 : Rf< 8, "F8">; -def F9 : Rf< 9, "F9">; def F10 : Rf<10, "F10">; def F11 : Rf<11, "F11">; -def F12 : Rf<12, "F12">; def F13 : Rf<13, "F13">; def F14 : Rf<14, "F14">; -def F15 : Rf<15, "F15">; def F16 : Rf<16, "F16">; def F17 : Rf<17, "F17">; -def F18 : Rf<18, "F18">; def F19 : Rf<19, "F19">; def F20 : Rf<20, "F20">; -def F21 : Rf<21, "F21">; def F22 : Rf<22, "F22">; def F23 : Rf<23, "F23">; -def F24 : Rf<24, "F24">; def F25 : Rf<25, "F25">; def F26 : Rf<26, "F26">; -def F27 : Rf<27, "F27">; def F28 : Rf<28, "F28">; def F29 : Rf<29, "F29">; -def F30 : Rf<30, "F30">; def F31 : Rf<31, "F31">; +def F0 : Rf< 0, "F0">, DwarfRegNum<32>; +def F1 : Rf< 1, "F1">, DwarfRegNum<33>; +def F2 : Rf< 2, "F2">, DwarfRegNum<34>; +def F3 : Rf< 3, "F3">, DwarfRegNum<35>; +def F4 : Rf< 4, "F4">, DwarfRegNum<36>; +def F5 : Rf< 5, "F5">, DwarfRegNum<37>; +def F6 : Rf< 6, "F6">, DwarfRegNum<38>; +def F7 : Rf< 7, "F7">, DwarfRegNum<39>; +def F8 : Rf< 8, "F8">, DwarfRegNum<40>; +def F9 : Rf< 9, "F9">, DwarfRegNum<41>; +def F10 : Rf<10, "F10">, DwarfRegNum<42>; +def F11 : Rf<11, "F11">, DwarfRegNum<43>; +def F12 : Rf<12, "F12">, DwarfRegNum<44>; +def F13 : Rf<13, "F13">, DwarfRegNum<45>; +def F14 : Rf<14, "F14">, DwarfRegNum<46>; +def F15 : Rf<15, "F15">, DwarfRegNum<47>; +def F16 : Rf<16, "F16">, DwarfRegNum<48>; +def F17 : Rf<17, "F17">, DwarfRegNum<49>; +def F18 : Rf<18, "F18">, DwarfRegNum<50>; +def F19 : Rf<19, "F19">, DwarfRegNum<51>; +def F20 : Rf<20, "F20">, DwarfRegNum<52>; +def F21 : Rf<21, "F21">, DwarfRegNum<53>; +def F22 : Rf<22, "F22">, DwarfRegNum<54>; +def F23 : Rf<23, "F23">, DwarfRegNum<55>; +def F24 : Rf<24, "F24">, DwarfRegNum<56>; +def F25 : Rf<25, "F25">, DwarfRegNum<57>; +def F26 : Rf<26, "F26">, DwarfRegNum<58>; +def F27 : Rf<27, "F27">, DwarfRegNum<59>; +def F28 : Rf<28, "F28">, DwarfRegNum<60>; +def F29 : Rf<29, "F29">, DwarfRegNum<61>; +def F30 : Rf<30, "F30">, DwarfRegNum<62>; +def F31 : Rf<31, "F31">, DwarfRegNum<63>; // Aliases of the F* registers used to hold 64-bit fp values (doubles) -def D0 : Rd< 0, "F0", [F0, F1]>; def D1 : Rd< 2, "F2", [F2, F3]>; -def D2 : Rd< 4, "F4", [F4, F5]>; def D3 : Rd< 6, "F6", [F6, F7]>; -def D4 : Rd< 8, "F8", [F8, F9]>; def D5 : Rd<10, "F10", [F10, F11]>; -def D6 : Rd<12, "F12", [F12, F13]>; def D7 : Rd<14, "F14", [F14, F15]>; -def D8 : Rd<16, "F16", [F16, F17]>; def D9 : Rd<18, "F18", [F18, F19]>; -def D10 : Rd<20, "F20", [F20, F21]>; def D11 : Rd<22, "F22", [F22, F23]>; -def D12 : Rd<24, "F24", [F24, F25]>; def D13 : Rd<26, "F26", [F26, F27]>; -def D14 : Rd<28, "F28", [F28, F29]>; def D15 : Rd<30, "F30", [F30, F31]>; +def D0 : Rd< 0, "F0", [F0, F1]>, DwarfRegNum<32>; +def D1 : Rd< 2, "F2", [F2, F3]>, DwarfRegNum<33>; +def D2 : Rd< 4, "F4", [F4, F5]>, DwarfRegNum<34>; +def D3 : Rd< 6, "F6", [F6, F7]>, DwarfRegNum<35>; +def D4 : Rd< 8, "F8", [F8, F9]>, DwarfRegNum<36>; +def D5 : Rd<10, "F10", [F10, F11]>, DwarfRegNum<37>; +def D6 : Rd<12, "F12", [F12, F13]>, DwarfRegNum<38>; +def D7 : Rd<14, "F14", [F14, F15]>, DwarfRegNum<39>; +def D8 : Rd<16, "F16", [F16, F17]>, DwarfRegNum<40>; +def D9 : Rd<18, "F18", [F18, F19]>, DwarfRegNum<41>; +def D10 : Rd<20, "F20", [F20, F21]>, DwarfRegNum<42>; +def D11 : Rd<22, "F22", [F22, F23]>, DwarfRegNum<43>; +def D12 : Rd<24, "F24", [F24, F25]>, DwarfRegNum<44>; +def D13 : Rd<26, "F26", [F26, F27]>, DwarfRegNum<45>; +def D14 : Rd<28, "F28", [F28, F29]>, DwarfRegNum<46>; +def D15 : Rd<30, "F30", [F30, F31]>, DwarfRegNum<47>; // Register classes. // _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits