Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.150 -> 1.151
X86ISelLowering.h updated: 1.49 -> 1.50
X86InstrSSE.td updated: 1.52 -> 1.53
---
Log message:
Use a X86 target specific node X86ISD::PINSRW instead of a mal-formed
INSERT_VECTOR_ELT to insert a 16-bit value in a 128-bit vector.
---
Diffs of the changes: (+12 -6)
X86ISelLowering.cpp | 3 ++-
X86ISelLowering.h | 6 +++++-
X86InstrSSE.td | 9 +++++----
3 files changed, 12 insertions(+), 6 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.150
llvm/lib/Target/X86/X86ISelLowering.cpp:1.151
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.150 Fri Mar 31 13:22:53 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Fri Mar 31 15:55:24 2006
@@ -2685,7 +2685,7 @@
N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
if (N2.getValueType() != MVT::i32)
N2 = DAG.getConstant(cast<ConstantSDNode>(N2)->getValue(), MVT::i32);
- return DAG.getNode(ISD::INSERT_VECTOR_ELT, VT, Op.getOperand(0), N1, N2);
+ return DAG.getNode(X86ISD::PINSRW, VT, Op.getOperand(0), N1, N2);
}
return SDOperand();
@@ -2726,6 +2726,7 @@
case X86ISD::S2VEC: return "X86ISD::S2VEC";
case X86ISD::ZEXT_S2VEC: return "X86ISD::ZEXT_S2VEC";
case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
+ case X86ISD::PINSRW: return "X86ISD::PINSRW";
}
}
Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.49
llvm/lib/Target/X86/X86ISelLowering.h:1.50
--- llvm/lib/Target/X86/X86ISelLowering.h:1.49 Fri Mar 31 13:22:53 2006
+++ llvm/lib/Target/X86/X86ISelLowering.h Fri Mar 31 15:55:24 2006
@@ -155,8 +155,12 @@
ZEXT_S2VEC,
/// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
- /// i32, corresponds to X86::PINSRW.
+ /// i32, corresponds to X86::PEXTRW.
PEXTRW,
+
+ /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
+ /// corresponds to X86::PINSRW.
+ PINSRW,
};
// X86 specific condition code. These correspond to X86_*_COND in
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.52
llvm/lib/Target/X86/X86InstrSSE.td:1.53
--- llvm/lib/Target/X86/X86InstrSSE.td:1.52 Fri Mar 31 15:29:33 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Fri Mar 31 15:55:24 2006
@@ -27,9 +27,10 @@
SDTypeProfile<1, 1, []>, []>;
def X86zexts2vec : SDNode<"X86ISD::ZEXT_S2VEC",
SDTypeProfile<1, 1, []>, []>;
-
def X86pextrw : SDNode<"X86ISD::PEXTRW",
SDTypeProfile<1, 2, []>, []>;
+def X86pinsrw : SDNode<"X86ISD::PINSRW",
+ SDTypeProfile<1, 3, []>, []>;
//===----------------------------------------------------------------------===//
// SSE pattern fragments
@@ -1468,13 +1469,13 @@
def PINSRWrr : PDIi8<0xC4, MRMSrcReg,
(ops VR128:$dst, VR128:$src1, R32:$src2, i32i8imm:$src3),
"pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
- [(set VR128:$dst, (v8i16 (vector_insert (v8i16
VR128:$src1),
- R32:$src2, (i32 imm:$src3))))]>;
+ [(set VR128:$dst, (v8i16 (X86pinsrw (v8i16 VR128:$src1),
+ R32:$src2, (i32 imm:$src3))))]>;
def PINSRWrm : PDIi8<0xC4, MRMSrcMem,
(ops VR128:$dst, VR128:$src1, i16mem:$src2,
i32i8imm:$src3),
"pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
[(set VR128:$dst,
- (v8i16 (vector_insert (v8i16 VR128:$src1),
+ (v8i16 (X86pinsrw (v8i16 VR128:$src1),
(i32 (anyext (loadi16 addr:$src2))),
(i32 imm:$src3))))]>;
}
_______________________________________________
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
