[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.199 -> 1.200
---
Log message:

Teach the X86 backend about non-i32 inline asm register classes.


---
Diffs of the changes:  (+25 -5)

 X86ISelLowering.cpp |   30 +++++++++++++++++++++++++-----
 1 files changed, 25 insertions(+), 5 deletions(-)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.199 
llvm/lib/Target/X86/X86ISelLowering.cpp:1.200
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.199       Fri May  5 16:35:18 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp     Fri May  5 19:29:37 2006
@@ -3998,14 +3998,34 @@
     default: break;  // Unknown constriant letter
     case 'r':   // GENERAL_REGS
     case 'R':   // LEGACY_REGS
-      return make_vector<unsigned>(X86::EAX, X86::EBX, X86::ECX, X86::EDX,
-                                   X86::ESI, X86::EDI, X86::EBP, X86::ESP, 0);
+      if (VT == MVT::i32)
+        return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
+                                     X86::ESI, X86::EDI, X86::EBP, X86::ESP, 
0);
+      else if (VT == MVT::i16)
+        return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 
+                                     X86::SI, X86::DI, X86::BP, X86::SP, 0);
+      else if (VT == MVT::i8)
+        return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::DL, 0);
+      break;
     case 'l':   // INDEX_REGS
-      return make_vector<unsigned>(X86::EAX, X86::EBX, X86::ECX, X86::EDX,
-                                   X86::ESI, X86::EDI, X86::EBP, 0);
+      if (VT == MVT::i32)
+        return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
+                                     X86::ESI, X86::EDI, X86::EBP, 0);
+      else if (VT == MVT::i16)
+        return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 
+                                     X86::SI, X86::DI, X86::BP, 0);
+      else if (VT == MVT::i8)
+        return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::DL, 0);
+      break;
     case 'q':   // Q_REGS (GENERAL_REGS in 64-bit mode)
     case 'Q':   // Q_REGS
-      return make_vector<unsigned>(X86::EAX, X86::EBX, X86::ECX, X86::EDX, 0);
+      if (VT == MVT::i32)
+        return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 
0);
+      else if (VT == MVT::i16)
+        return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
+      else if (VT == MVT::i8)
+        return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::DL, 0);
+        break;
     case 'x':   // SSE_REGS if SSE1 allowed
       if (Subtarget->hasSSE1())
         return make_vector<unsigned>(X86::XMM0, X86::XMM1, X86::XMM2, 
X86::XMM3,



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