Changes in directory llvm/lib/Target/IA64:
IA64ISelLowering.cpp updated: 1.37 -> 1.38
---
Log message:
Change RET node to include signness information of the return values. i.e.
RET chain, value1, sign1, value2, sign2, ...
---
Diffs of the changes: (+1 -1)
IA64ISelLowering.cpp | 2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Target/IA64/IA64ISelLowering.cpp
diff -u llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.37
llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.38
--- llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.37 Sat Apr 22 13:53:45 2006
+++ llvm/lib/Target/IA64/IA64ISelLowering.cpp Fri May 26 18:10:12 2006
@@ -562,7 +562,7 @@
AR_PFSVal = DAG.getCopyToReg(AR_PFSVal.getValue(1), IA64::AR_PFS,
AR_PFSVal);
return DAG.getNode(IA64ISD::RET_FLAG, MVT::Other, AR_PFSVal);
- case 2: {
+ case 3: {
// Copy the result into the output register & restore ar.pfs
MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
unsigned ArgReg = MVT::isInteger(ArgVT) ? IA64::r8 : IA64::F8;
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