Changes in directory llvm/lib/Target/X86:
X86ISelDAGToDAG.cpp updated: 1.73 -> 1.74
---
Log message:
Add support for "m" inline asm constraints.
---
Diffs of the changes: (+29 -1)
X86ISelDAGToDAG.cpp | 30 +++++++++++++++++++++++++++++-
1 files changed, 29 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.73
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.74
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.73 Fri Jun 2 17:38:37 2006
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Thu Jun 8 13:03:49 2006
@@ -128,7 +128,13 @@
bool TryFoldLoad(SDOperand P, SDOperand N,
SDOperand &Base, SDOperand &Scale,
SDOperand &Index, SDOperand &Disp);
-
+ /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
+ /// inline asm expressions.
+ virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
+ char ConstraintCode,
+ std::vector<SDOperand> &OutOps,
+ SelectionDAG &DAG);
+
void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI);
inline void getAddressOperands(X86ISelAddressMode &AM, SDOperand &Base,
@@ -876,6 +882,28 @@
#endif
}
+bool X86DAGToDAGISel::
+SelectInlineAsmMemoryOperand(const SDOperand &Op, char ConstraintCode,
+ std::vector<SDOperand> &OutOps, SelectionDAG
&DAG){
+ SDOperand Op0, Op1, Op2, Op3;
+ switch (ConstraintCode) {
+ case 'o': // offsetable ??
+ case 'v': // not offsetable ??
+ default: return true;
+ case 'm': // memory
+ if (!SelectAddr(Op, Op0, Op1, Op2, Op3))
+ return true;
+ break;
+ }
+
+ OutOps.resize(4);
+ Select(OutOps[0], Op0);
+ Select(OutOps[1], Op1);
+ Select(OutOps[2], Op2);
+ Select(OutOps[3], Op3);
+ return false;
+}
+
/// createX86ISelDag - This pass converts a legalized DAG into a
/// X86-specific DAG, ready for instruction scheduling.
///
_______________________________________________
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
