Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.256 -> 1.257 --- Log message: Consistency. EXTRACT_ELEMENT index operand should have ptr type. --- Diffs of the changes: (+13 -10) SelectionDAGISel.cpp | 23 +++++++++++++---------- 1 files changed, 13 insertions(+), 10 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.256 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.257 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.256 Mon Jun 12 13:25:29 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Jun 15 03:11:54 2006 @@ -136,7 +136,8 @@ /// specified value into the registers specified by this object. This uses /// Chain/Flag as the input and updates them for the output Chain/Flag. void getCopyToRegs(SDOperand Val, SelectionDAG &DAG, - SDOperand &Chain, SDOperand &Flag) const; + SDOperand &Chain, SDOperand &Flag, + MVT::ValueType PtrVT) const; /// AddInlineAsmOperands - Add this value to the specified inlineasm node /// operand list. This adds the code marker and includes the number of @@ -1800,7 +1801,8 @@ /// specified value into the registers specified by this object. This uses /// Chain/Flag as the input and updates them for the output Chain/Flag. void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG, - SDOperand &Chain, SDOperand &Flag) const { + SDOperand &Chain, SDOperand &Flag, + MVT::ValueType PtrVT) const { if (Regs.size() == 1) { // If there is a single register and the types differ, this must be // a promotion. @@ -1822,7 +1824,7 @@ for (unsigned i = 0, e = R.size(); i != e; ++i) { SDOperand Part = DAG.getNode(ISD::EXTRACT_ELEMENT, RegVT, Val, - DAG.getConstant(i, MVT::i32)); + DAG.getConstant(i, PtrVT)); Chain = DAG.getCopyToReg(Chain, R[i], Part, Flag); Flag = Chain.getValue(1); } @@ -2184,7 +2186,8 @@ } // Use the produced MatchedRegs object to - MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag); + MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag, + TLI.getPointerTy()); MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands); break; } @@ -2232,7 +2235,7 @@ // FIXME: should be match fail. assert(!InRegs.Regs.empty() && "Couldn't allocate input reg!"); - InRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag); + InRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag, TLI.getPointerTy()); InRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, AsmNodeOperands); break; @@ -3300,7 +3303,7 @@ SDOperand Root = SDL.getRoot(); for (unsigned i = 0; i != NE; ++i) { SDOperand Elt = DAG.getNode(ISD::VEXTRACT_VECTOR_ELT, PTyElementVT, - Op, DAG.getConstant(i, MVT::i32)); + Op, DAG.getConstant(i, TLI.getPointerTy())); if (PTyElementVT == PTyLegalElementVT) { // Elements are legal. OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt)); @@ -3315,9 +3318,9 @@ // Elements are expanded. // The src value is expanded into multiple registers. SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT, - Elt, DAG.getConstant(0, MVT::i32)); + Elt, DAG.getConstant(0, TLI.getPointerTy())); SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT, - Elt, DAG.getConstant(1, MVT::i32)); + Elt, DAG.getConstant(1, TLI.getPointerTy())); OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Lo)); OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Hi)); } @@ -3333,9 +3336,9 @@ } else { // The src value is expanded into multiple registers. SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT, - Op, DAG.getConstant(0, MVT::i32)); + Op, DAG.getConstant(0, TLI.getPointerTy())); SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT, - Op, DAG.getConstant(1, MVT::i32)); + Op, DAG.getConstant(1, TLI.getPointerTy())); Op = DAG.getCopyToReg(SDL.getRoot(), Reg, Lo); return DAG.getCopyToReg(Op, Reg+1, Hi); } _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits