Changes in directory llvm/lib/Target/ARM:
ARM.h updated: 1.2 -> 1.3 ARMISelDAGToDAG.cpp updated: 1.35 -> 1.36 ARMInstrInfo.td updated: 1.20 -> 1.21 --- Log message: add the "eq" condition code implement a movcond instruction --- Diffs of the changes: (+13 -8) ARM.h | 4 +++- ARMISelDAGToDAG.cpp | 6 +++--- ARMInstrInfo.td | 11 +++++++---- 3 files changed, 13 insertions(+), 8 deletions(-) Index: llvm/lib/Target/ARM/ARM.h diff -u llvm/lib/Target/ARM/ARM.h:1.2 llvm/lib/Target/ARM/ARM.h:1.3 --- llvm/lib/Target/ARM/ARM.h:1.2 Thu Aug 24 11:13:15 2006 +++ llvm/lib/Target/ARM/ARM.h Thu Aug 24 12:19:08 2006 @@ -23,7 +23,8 @@ // Enums corresponding to ARM condition codes namespace ARMCC { enum CondCodes { - NE + NE, + EQ }; } @@ -31,6 +32,7 @@ switch (CC) { default: assert(0 && "Unknown condition code"); case ARMCC::NE: return "ne"; + case ARMCC::EQ: return "eq"; } } Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp diff -u llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.35 llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.36 --- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.35 Thu Aug 24 11:13:15 2006 +++ llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp Thu Aug 24 12:19:08 2006 @@ -84,6 +84,7 @@ switch (CC) { default: assert(0 && "Unknown condition code!"); case ISD::SETNE: return ARMCC::NE; + case ISD::SETEQ: return ARMCC::EQ; } } @@ -317,11 +318,10 @@ ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); SDOperand TrueVal = Op.getOperand(2); SDOperand FalseVal = Op.getOperand(3); - - assert(CC == ISD::SETEQ); + SDOperand ARMCC = DAG.getConstant(DAGCCToARMCC(CC), MVT::i32); SDOperand Cmp = DAG.getNode(ARMISD::CMP, MVT::Flag, LHS, RHS); - return DAG.getNode(ARMISD::SELECT, MVT::i32, FalseVal, TrueVal, Cmp); + return DAG.getNode(ARMISD::SELECT, MVT::i32, FalseVal, TrueVal, ARMCC, Cmp); } static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG) { Index: llvm/lib/Target/ARM/ARMInstrInfo.td diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.20 llvm/lib/Target/ARM/ARMInstrInfo.td:1.21 --- llvm/lib/Target/ARM/ARMInstrInfo.td:1.20 Thu Aug 24 11:13:15 2006 +++ llvm/lib/Target/ARM/ARMInstrInfo.td Thu Aug 24 12:19:08 2006 @@ -54,7 +54,10 @@ [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; def retflag : SDNode<"ARMISD::RET_FLAG", SDTRet, [SDNPHasChain, SDNPOptInFlag]>; -def armselect : SDNode<"ARMISD::SELECT", SDTIntBinOp, [SDNPInFlag, SDNPOutFlag]>; + +def SDTarmselect : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisVT<2, i32>]>; + +def armselect : SDNode<"ARMISD::SELECT", SDTarmselect, [SDNPInFlag, SDNPOutFlag]>; def SDTarmbr : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; def armbr : SDNode<"ARMISD::BR", SDTarmbr, [SDNPHasChain, SDNPInFlag]>; @@ -111,9 +114,9 @@ [(set IntRegs:$dst, (and IntRegs:$a, IntRegs:$b))]>; let isTwoAddress = 1 in { - def moveq : InstARM<(ops IntRegs:$dst, IntRegs:$false, IntRegs:$true), - "moveq $dst, $true", - [(set IntRegs:$dst, (armselect IntRegs:$true, IntRegs:$false))]>; + def movcond : InstARM<(ops IntRegs:$dst, IntRegs:$false, IntRegs:$true, CCOp:$cc), + "mov$cc $dst, $true", + [(set IntRegs:$dst, (armselect IntRegs:$true, IntRegs:$false, imm:$cc))]>; } def bcond : InstARM<(ops brtarget:$dst, CCOp:$cc), _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits