Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.td updated: 1.52 -> 1.53
---
Log message:
define the IntBinOp class and use it to implement the multiply instructions
---
Diffs of the changes: (+13 -12)
ARMInstrInfo.td | 25 +++++++++++++------------
1 files changed, 13 insertions(+), 12 deletions(-)
Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.52
llvm/lib/Target/ARM/ARMInstrInfo.td:1.53
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.52 Mon Oct 16 12:38:12 2006
+++ llvm/lib/Target/ARM/ARMInstrInfo.td Mon Oct 16 12:57:20 2006
@@ -36,9 +36,8 @@
//def raddr : ComplexPattern<iPTR, 2, "SelectAddrRegReg", [], []>;
//===----------------------------------------------------------------------===//
-// Instructions
+// Instruction Class Templates
//===----------------------------------------------------------------------===//
-
class InstARM<dag ops, string asmstr, list<dag> pattern> : Instruction {
let Namespace = "ARM";
@@ -47,6 +46,15 @@
let Pattern = pattern;
}
+class IntBinOp<string OpcStr, SDNode OpNode> :
+ InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
+ !strconcat(OpcStr, " $dst, $a, $b"),
+ [(set IntRegs:$dst, (OpNode IntRegs:$a, IntRegs:$b))]>;
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
def brtarget : Operand<OtherVT>;
// Operand for printing out a condition code.
@@ -186,18 +194,11 @@
IntRegs:$false, imm:$cc))]>;
}
-def MUL : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
- "mul $dst, $a, $b",
- [(set IntRegs:$dst, (mul IntRegs:$a, IntRegs:$b))]>;
+def MUL : IntBinOp<"mul", mul>;
let Defs = [R0] in {
- def SMULL : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
- "smull r12, $dst, $a, $b",
- [(set IntRegs:$dst, (mulhs IntRegs:$a, IntRegs:$b))]>;
-
- def UMULL : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
- "umull r12, $dst, $a, $b",
- [(set IntRegs:$dst, (mulhu IntRegs:$a, IntRegs:$b))]>;
+ def SMULL : IntBinOp<"smull r12,", mulhs>;
+ def UMULL : IntBinOp<"umull r12,", mulhu>;
}
def bcond : InstARM<(ops brtarget:$dst, CCOp:$cc),
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