Changes in directory llvm/lib/Target/X86:
X86FloatingPoint.cpp updated: 1.60 -> 1.61 X86ISelDAGToDAG.cpp updated: 1.129 -> 1.130 X86ISelLowering.cpp updated: 1.294 -> 1.295 X86InstrInfo.cpp updated: 1.74 -> 1.75 X86RegisterInfo.cpp updated: 1.180 -> 1.181 --- Log message: Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead of opcode and number of operands. --- Diffs of the changes: (+75 -61) X86FloatingPoint.cpp | 19 ++++++++++++++----- X86ISelDAGToDAG.cpp | 19 ++++++++++--------- X86ISelLowering.cpp | 22 +++++++++++++--------- X86InstrInfo.cpp | 30 +++++++++++++++--------------- X86RegisterInfo.cpp | 46 +++++++++++++++++++++++----------------------- 5 files changed, 75 insertions(+), 61 deletions(-) Index: llvm/lib/Target/X86/X86FloatingPoint.cpp diff -u llvm/lib/Target/X86/X86FloatingPoint.cpp:1.60 llvm/lib/Target/X86/X86FloatingPoint.cpp:1.61 --- llvm/lib/Target/X86/X86FloatingPoint.cpp:1.60 Wed Nov 15 14:56:39 2006 +++ llvm/lib/Target/X86/X86FloatingPoint.cpp Mon Nov 27 17:37:22 2006 @@ -107,6 +107,9 @@ bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; } void moveToTop(unsigned RegNo, MachineBasicBlock::iterator &I) { if (!isAtTop(RegNo)) { + MachineFunction *MF = I->getParent()->getParent(); + const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); + unsigned STReg = getSTReg(RegNo); unsigned RegOnTop = getStackEntry(0); @@ -118,16 +121,18 @@ std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]); // Emit an fxch to update the runtime processors version of the state - BuildMI(*MBB, I, X86::FXCH, 1).addReg(STReg); + BuildMI(*MBB, I, TII.get(X86::FXCH)).addReg(STReg); NumFXCH++; } } void duplicateToTop(unsigned RegNo, unsigned AsReg, MachineInstr *I) { + MachineFunction *MF = I->getParent()->getParent(); + const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); unsigned STReg = getSTReg(RegNo); pushReg(AsReg); // New register on top of stack - BuildMI(*MBB, I, X86::FLDrr, 1).addReg(STReg); + BuildMI(*MBB, I, TII.get(X86::FLDrr)).addReg(STReg); } // popStackAfter - Pop the current value off of the top of the FP stack @@ -435,7 +440,9 @@ I->RemoveOperand(0); } else { // Insert an explicit pop - I = BuildMI(*MBB, ++I, X86::FSTPrr, 1).addReg(X86::ST0); + MachineFunction *MF = I->getParent()->getParent(); + const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); + I = BuildMI(*MBB, ++I, TII.get(X86::FSTPrr)).addReg(X86::ST0); } } @@ -459,7 +466,9 @@ RegMap[TopReg] = OldSlot; RegMap[FPRegNo] = ~0; Stack[--StackTop] = ~0; - I = BuildMI(*MBB, ++I, X86::FSTPrr, 1).addReg(STReg); + MachineFunction *MF = I->getParent()->getParent(); + const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); + I = BuildMI(*MBB, ++I, TII.get(X86::FSTPrr)).addReg(STReg); } @@ -697,7 +706,7 @@ // Replace the old instruction with a new instruction MBB->remove(I++); - I = BuildMI(*MBB, I, Opcode, 1).addReg(getSTReg(NotTOS)); + I = BuildMI(*MBB, I, TII.get(Opcode)).addReg(getSTReg(NotTOS)); // If both operands are killed, pop one off of the stack in addition to // overwriting the other one. Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp diff -u llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.129 llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.130 --- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp:1.129 Fri Nov 17 16:10:14 2006 +++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Mon Nov 27 17:37:22 2006 @@ -525,7 +525,8 @@ // Finally, if we found any FP code, emit the FP_REG_KILL instruction. if (ContainsFPCode) { - BuildMI(*BB, BB->getFirstTerminator(), X86::FP_REG_KILL, 0); + BuildMI(*BB, BB->getFirstTerminator(), + TM.getInstrInfo()->get(X86::FP_REG_KILL)); ++NumFPKill; } } @@ -535,19 +536,20 @@ /// the main function. void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI) { + const TargetInstrInfo *TII = TM.getInstrInfo(); if (Subtarget->isTargetCygwin()) - BuildMI(BB, X86::CALLpcrel32, 1).addExternalSymbol("__main"); + BuildMI(BB, TII->get(X86::CALLpcrel32)).addExternalSymbol("__main"); // Switch the FPU to 64-bit precision mode for better compatibility and speed. int CWFrameIdx = MFI->CreateStackObject(2, 2); - addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx); + addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx); // Set the high part to be 64-bit precision. - addFrameReference(BuildMI(BB, X86::MOV8mi, 5), + addFrameReference(BuildMI(BB, TII->get(X86::MOV8mi)), CWFrameIdx, 1).addImm(2); // Reload the modified control word now. - addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx); + addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx); } void X86DAGToDAGISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) { @@ -943,11 +945,10 @@ MachineBasicBlock &FirstMBB = BB->getParent()->front(); MachineBasicBlock::iterator MBBI = FirstMBB.begin(); SSARegMap *RegMap = BB->getParent()->getSSARegMap(); - // FIXME: when we get to LP64, we will need to create the appropriate - // type of register here. GlobalBaseReg = RegMap->createVirtualRegister(X86::GR32RegisterClass); - BuildMI(FirstMBB, MBBI, X86::MovePCtoStack, 0); - BuildMI(FirstMBB, MBBI, X86::POP32r, 1, GlobalBaseReg); + const TargetInstrInfo *TII = TM.getInstrInfo(); + BuildMI(FirstMBB, MBBI, TII->get(X86::MovePCtoStack)); + BuildMI(FirstMBB, MBBI, TII->get(X86::POP32r), GlobalBaseReg); } return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).Val; } Index: llvm/lib/Target/X86/X86ISelLowering.cpp diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.294 llvm/lib/Target/X86/X86ISelLowering.cpp:1.295 --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.294 Mon Nov 20 18:01:06 2006 +++ llvm/lib/Target/X86/X86ISelLowering.cpp Mon Nov 27 17:37:22 2006 @@ -5036,6 +5036,7 @@ MachineBasicBlock * X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, MachineBasicBlock *BB) { + const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); switch (MI->getOpcode()) { default: assert(false && "Unexpected instr type to insert"); case X86::CMOV_FR32: @@ -5062,7 +5063,7 @@ MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); unsigned Opc = X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); - BuildMI(BB, Opc, 1).addMBB(sinkMBB); + BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB); MachineFunction *F = BB->getParent(); F->getBasicBlockList().insert(It, copy0MBB); F->getBasicBlockList().insert(It, sinkMBB); @@ -5090,7 +5091,7 @@ // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] // ... BB = sinkMBB; - BuildMI(BB, X86::PHI, 4, MI->getOperand(0).getReg()) + BuildMI(BB, TII->get(X86::PHI), MI->getOperand(0).getReg()) .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); @@ -5105,21 +5106,23 @@ // mode when truncating to an integer value. MachineFunction *F = BB->getParent(); int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2); - addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx); + addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx); // Load the old value of the high byte of the control word... unsigned OldCW = F->getSSARegMap()->createVirtualRegister(X86::GR16RegisterClass); - addFrameReference(BuildMI(BB, X86::MOV16rm, 4, OldCW), CWFrameIdx); + addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx); // Set the high part to be round to zero... - addFrameReference(BuildMI(BB, X86::MOV16mi, 5), CWFrameIdx).addImm(0xC7F); + addFrameReference(BuildMI(BB, TII->get(X86::MOV16mi)), CWFrameIdx) + .addImm(0xC7F); // Reload the modified control word now... - addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx); + addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx); // Restore the memory image of control word to original value - addFrameReference(BuildMI(BB, X86::MOV16mr, 5), CWFrameIdx).addReg(OldCW); + addFrameReference(BuildMI(BB, TII->get(X86::MOV16mr)), CWFrameIdx) + .addReg(OldCW); // Get the X86 opcode to use. unsigned Opc; @@ -5151,10 +5154,11 @@ } else { AM.Disp = Op.getImm(); } - addFullAddress(BuildMI(BB, Opc, 5), AM).addReg(MI->getOperand(4).getReg()); + addFullAddress(BuildMI(BB, TII->get(Opc)), AM) + .addReg(MI->getOperand(4).getReg()); // Reload the original control word now. - addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx); + addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx); delete MI; // The pseudo instruction is gone now. return BB; Index: llvm/lib/Target/X86/X86InstrInfo.cpp diff -u llvm/lib/Target/X86/X86InstrInfo.cpp:1.74 llvm/lib/Target/X86/X86InstrInfo.cpp:1.75 --- llvm/lib/Target/X86/X86InstrInfo.cpp:1.74 Thu Nov 16 17:22:26 2006 +++ llvm/lib/Target/X86/X86InstrInfo.cpp Mon Nov 27 17:37:22 2006 @@ -139,7 +139,7 @@ unsigned C = MI->getOperand(2).getReg(); unsigned M = MI->getOperand(3).getImmedValue(); if (!Subtarget->hasSSE2() || B != C) return 0; - NewMI = BuildMI(*this, X86::PSHUFDri, 2, A).addReg(B).addImm(M); + NewMI = BuildMI(get(X86::PSHUFDri), A).addReg(B).addImm(M); NewMI->copyKillDeadInfo(MI); return NewMI; } @@ -158,41 +158,41 @@ case X86::INC32r: case X86::INC64_32r: assert(MI->getNumOperands() == 2 && "Unknown inc instruction!"); - NewMI = addRegOffset(BuildMI(*this, X86::LEA32r, 5, Dest), Src, 1); + NewMI = addRegOffset(BuildMI(get(X86::LEA32r), Dest), Src, 1); break; case X86::INC16r: case X86::INC64_16r: if (DisableLEA16) return 0; assert(MI->getNumOperands() == 2 && "Unknown inc instruction!"); - NewMI = addRegOffset(BuildMI(*this, X86::LEA16r, 5, Dest), Src, 1); + NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, 1); break; case X86::DEC32r: case X86::DEC64_32r: assert(MI->getNumOperands() == 2 && "Unknown dec instruction!"); - NewMI = addRegOffset(BuildMI(*this, X86::LEA32r, 5, Dest), Src, -1); + NewMI = addRegOffset(BuildMI(get(X86::LEA32r), Dest), Src, -1); break; case X86::DEC16r: case X86::DEC64_16r: if (DisableLEA16) return 0; assert(MI->getNumOperands() == 2 && "Unknown dec instruction!"); - NewMI = addRegOffset(BuildMI(*this, X86::LEA16r, 5, Dest), Src, -1); + NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, -1); break; case X86::ADD32rr: assert(MI->getNumOperands() == 3 && "Unknown add instruction!"); - NewMI = addRegReg(BuildMI(*this, X86::LEA32r, 5, Dest), Src, + NewMI = addRegReg(BuildMI(get(X86::LEA32r), Dest), Src, MI->getOperand(2).getReg()); break; case X86::ADD16rr: if (DisableLEA16) return 0; assert(MI->getNumOperands() == 3 && "Unknown add instruction!"); - NewMI = addRegReg(BuildMI(*this, X86::LEA16r, 5, Dest), Src, + NewMI = addRegReg(BuildMI(get(X86::LEA16r), Dest), Src, MI->getOperand(2).getReg()); break; case X86::ADD32ri: case X86::ADD32ri8: assert(MI->getNumOperands() == 3 && "Unknown add instruction!"); if (MI->getOperand(2).isImmediate()) - NewMI = addRegOffset(BuildMI(*this, X86::LEA32r, 5, Dest), Src, + NewMI = addRegOffset(BuildMI(get(X86::LEA32r), Dest), Src, MI->getOperand(2).getImmedValue()); break; case X86::ADD16ri: @@ -200,7 +200,7 @@ if (DisableLEA16) return 0; assert(MI->getNumOperands() == 3 && "Unknown add instruction!"); if (MI->getOperand(2).isImmediate()) - NewMI = addRegOffset(BuildMI(*this, X86::LEA16r, 5, Dest), Src, + NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, MI->getOperand(2).getImmedValue()); break; case X86::SHL16ri: @@ -214,7 +214,7 @@ AM.Scale = 1 << ShAmt; AM.IndexReg = Src; unsigned Opc = MI->getOpcode() == X86::SHL32ri ? X86::LEA32r :X86::LEA16r; - NewMI = addFullAddress(BuildMI(*this, Opc, 5, Dest), AM); + NewMI = addFullAddress(BuildMI(get(Opc), Dest), AM); } break; } @@ -249,7 +249,7 @@ unsigned C = MI->getOperand(2).getReg(); bool BisKill = MI->getOperand(1).isKill(); bool CisKill = MI->getOperand(2).isKill(); - return BuildMI(*this, Opc, 3, A).addReg(C, false, false, CisKill) + return BuildMI(get(Opc), A).addReg(C, false, false, CisKill) .addReg(B, false, false, BisKill).addImm(Size-Amt); } default: @@ -416,19 +416,19 @@ if (FBB == 0) { // One way branch. if (Cond.empty()) { // Unconditional branch? - BuildMI(&MBB, X86::JMP, 1).addMBB(TBB); + BuildMI(&MBB, get(X86::JMP)).addMBB(TBB); } else { // Conditional branch. unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm()); - BuildMI(&MBB, Opc, 1).addMBB(TBB); + BuildMI(&MBB, get(Opc)).addMBB(TBB); } return; } // Two-way Conditional branch. unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm()); - BuildMI(&MBB, Opc, 1).addMBB(TBB); - BuildMI(&MBB, X86::JMP, 1).addMBB(FBB); + BuildMI(&MBB, get(Opc)).addMBB(TBB); + BuildMI(&MBB, get(X86::JMP)).addMBB(FBB); } bool X86InstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const { Index: llvm/lib/Target/X86/X86RegisterInfo.cpp diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.180 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.181 --- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.180 Fri Nov 17 15:19:15 2006 +++ llvm/lib/Target/X86/X86RegisterInfo.cpp Mon Nov 27 17:37:22 2006 @@ -93,7 +93,7 @@ assert(0 && "Unknown regclass"); abort(); } - addFrameReference(BuildMI(MBB, MI, Opc, 5), FrameIdx).addReg(SrcReg); + addFrameReference(BuildMI(MBB, MI, TII.get(Opc)), FrameIdx).addReg(SrcReg); } void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, @@ -125,7 +125,7 @@ assert(0 && "Unknown regclass"); abort(); } - addFrameReference(BuildMI(MBB, MI, Opc, 4, DestReg), FrameIdx); + addFrameReference(BuildMI(MBB, MI, TII.get(Opc), DestReg), FrameIdx); } void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB, @@ -157,7 +157,7 @@ assert(0 && "Unknown regclass"); abort(); } - BuildMI(MBB, MI, Opc, 1, DestReg).addReg(SrcReg); + BuildMI(MBB, MI, TII.get(Opc), DestReg).addReg(SrcReg); } static MachineInstr *FuseTwoAddrInst(unsigned Opcode, unsigned FrameIndex, @@ -165,7 +165,7 @@ const TargetInstrInfo &TII) { unsigned NumOps = TII.getNumOperands(MI->getOpcode())-2; // Create the base instruction with the memory operand as the first part. - MachineInstrBuilder MIB = addFrameReference(BuildMI(TII, Opcode, 4+NumOps), + MachineInstrBuilder MIB = addFrameReference(BuildMI(TII.get(Opcode)), FrameIndex); // Loop over the rest of the ri operands, converting them over. @@ -188,7 +188,7 @@ static MachineInstr *FuseInst(unsigned Opcode, unsigned OpNo, unsigned FrameIndex, MachineInstr *MI, const TargetInstrInfo &TII) { - MachineInstrBuilder MIB = BuildMI(TII, Opcode, MI->getNumOperands()+3); + MachineInstrBuilder MIB = BuildMI(TII.get(Opcode)); for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); @@ -212,7 +212,7 @@ static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode, unsigned FrameIndex, MachineInstr *MI) { - return addFrameReference(BuildMI(TII, Opcode, 5), FrameIndex).addImm(0); + return addFrameReference(BuildMI(TII.get(Opcode)), FrameIndex).addImm(0); } @@ -908,7 +908,7 @@ MachineInstr *New = 0; if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) { - New=BuildMI(TII, Is64Bit ? X86::SUB64ri32 : X86::SUB32ri, 1, StackPtr) + New=BuildMI(TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri), StackPtr) .addReg(StackPtr).addImm(Amount); } else { assert(Old->getOpcode() == X86::ADJCALLSTACKUP); @@ -919,7 +919,7 @@ unsigned Opc = (Amount < 128) ? (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) : (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri); - New = BuildMI(TII, Opc, 1, StackPtr).addReg(StackPtr).addImm(Amount); + New = BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(Amount); } } @@ -935,7 +935,7 @@ (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) : (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri); MachineInstr *New = - BuildMI(TII, Opc, 1, StackPtr).addReg(StackPtr).addImm(CalleeAmt); + BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt); MBB.insert(I, New); } } @@ -1012,15 +1012,15 @@ // more than 4k bytes in one go. Touching the stack at 4K increments is // necessary to ensure that the guard pages used by the OS virtual memory // manager are allocated in correct sequence. - MI = BuildMI(TII, X86::MOV32ri, 2, X86::EAX).addImm(NumBytes); + MI = BuildMI(TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes); MBB.insert(MBBI, MI); - MI = BuildMI(TII, X86::CALLpcrel32, 1).addExternalSymbol("_alloca"); + MI = BuildMI(TII.get(X86::CALLpcrel32)).addExternalSymbol("_alloca"); MBB.insert(MBBI, MI); } else { unsigned Opc = (NumBytes < 128) ? (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) : (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri); - MI= BuildMI(TII, Opc, 1, StackPtr).addReg(StackPtr).addImm(NumBytes); + MI= BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(NumBytes); MBB.insert(MBBI, MI); } } @@ -1034,17 +1034,17 @@ // Save EBP into the appropriate stack slot... // mov [ESP-<offset>], EBP - MI = addRegOffset(BuildMI(TII, Is64Bit ? X86::MOV64mr : X86::MOV32mr, 5), + MI = addRegOffset(BuildMI(TII.get(Is64Bit ? X86::MOV64mr : X86::MOV32mr)), StackPtr, EBPOffset+NumBytes).addReg(FramePtr); MBB.insert(MBBI, MI); // Update EBP with the new base value... if (NumBytes == SlotSize) // mov EBP, ESP - MI = BuildMI(TII, Is64Bit ? X86::MOV64rr : X86::MOV32rr, 2, FramePtr). + MI = BuildMI(TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr). addReg(StackPtr); else // lea EBP, [ESP+StackSize] - MI = addRegOffset(BuildMI(TII, Is64Bit ? X86::LEA64r : X86::LEA32r, - 5, FramePtr), StackPtr, NumBytes-SlotSize); + MI = addRegOffset(BuildMI(TII.get(Is64Bit ? X86::LEA64r : X86::LEA32r), + FramePtr), StackPtr, NumBytes-SlotSize); MBB.insert(MBBI, MI); } @@ -1052,13 +1052,13 @@ // If it's main() on Cygwin\Mingw32 we should align stack as well if (Fn->hasExternalLinkage() && Fn->getName() == "main" && Subtarget->isTargetCygwin()) { - MI= BuildMI(TII, X86::AND32ri, 2, X86::ESP).addReg(X86::ESP).addImm(-Align); + MI= BuildMI(TII.get(X86::AND32ri), X86::ESP).addReg(X86::ESP).addImm(-Align); MBB.insert(MBBI, MI); // Probe the stack - MI = BuildMI(TII, X86::MOV32ri, 2, X86::EAX).addImm(Align); + MI = BuildMI(TII.get(X86::MOV32ri), X86::EAX).addImm(Align); MBB.insert(MBBI, MI); - MI = BuildMI(TII, X86::CALLpcrel32, 1).addExternalSymbol("_alloca"); + MI = BuildMI(TII.get(X86::CALLpcrel32)).addExternalSymbol("_alloca"); MBB.insert(MBBI, MI); } } @@ -1080,11 +1080,11 @@ if (hasFP(MF)) { // mov ESP, EBP - BuildMI(MBB, MBBI, Is64Bit ? X86::MOV64rr : X86::MOV32rr, 1, StackPtr). + BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr). addReg(FramePtr); // pop EBP - BuildMI(MBB, MBBI, Is64Bit ? X86::POP64r : X86::POP32r, 0, FramePtr); + BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr); } else { // Get the number of bytes allocated from the FrameInfo... unsigned NumBytes = MFI->getStackSize(); @@ -1112,12 +1112,12 @@ unsigned Opc = (NumBytes < 128) ? (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) : (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri); - BuildMI(MBB, MBBI, Opc, 2, StackPtr).addReg(StackPtr).addImm(NumBytes); + BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(NumBytes); } else if ((int)NumBytes < 0) { unsigned Opc = (-NumBytes < 128) ? (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) : (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri); - BuildMI(MBB, MBBI, Opc, 2, StackPtr).addReg(StackPtr).addImm(-NumBytes); + BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(-NumBytes); } } } _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits