Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.238 -> 1.239 --- Log message: 1. In ppc64 mode we need only use one GPR. 2. Float values need to be promoted to double when they are vararg. --- Diffs of the changes: (+7 -1) PPCISelLowering.cpp | 8 +++++++- 1 files changed, 7 insertions(+), 1 deletion(-) Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.238 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.239 --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.238 Thu Nov 30 19:45:39 2006 +++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Fri Dec 1 10:30:47 2006 @@ -1377,6 +1377,12 @@ break; case MVT::f32: case MVT::f64: + if (isVarArg && isPPC64) { + // Float varargs need to be promoted to double. + if (Arg.getValueType() == MVT::f32) + Arg = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Arg); + } + if (FPR_idx != NumFPRs) { RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg)); @@ -1390,7 +1396,7 @@ MemOpChains.push_back(Load.getValue(1)); RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); } - if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64) { + if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){ SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType()); PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour); SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0); _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits