Err, um, I meant 21164. dropping 21264 would be bad...
On 1/24/07, Andrew Lenharth <[EMAIL PROTECTED]> wrote: > > > Changes in directory llvm/lib/Target/Alpha: > > Alpha.td updated: 1.11 -> 1.12 > AlphaAsmPrinter.cpp updated: 1.61 -> 1.62 > AlphaISelDAGToDAG.cpp updated: 1.67 -> 1.68 > AlphaISelLowering.cpp updated: 1.76 -> 1.77 > AlphaISelLowering.h updated: 1.23 -> 1.24 > AlphaInstrInfo.td updated: 1.136 -> 1.137 > AlphaSubtarget.cpp updated: 1.7 -> 1.8 > AlphaSubtarget.h updated: 1.5 -> 1.6 > --- > Log message: > > FTOIT and ITOFT are bit converts, and if we drop 21264s, are always available > > --- > Diffs of the changes: (+17 -73) > > Alpha.td | 8 ++------ > AlphaAsmPrinter.cpp | 7 +++---- > AlphaISelDAGToDAG.cpp | 35 ++++------------------------------- > AlphaISelLowering.cpp | 27 ++++----------------------- > AlphaISelLowering.h | 2 +- > AlphaInstrInfo.td | 6 ++---- > AlphaSubtarget.cpp | 2 +- > AlphaSubtarget.h | 3 --- > 8 files changed, 17 insertions(+), 73 deletions(-) > > > Index: llvm/lib/Target/Alpha/Alpha.td > diff -u llvm/lib/Target/Alpha/Alpha.td:1.11 > llvm/lib/Target/Alpha/Alpha.td:1.12 > --- llvm/lib/Target/Alpha/Alpha.td:1.11 Wed May 17 19:11:53 2006 > +++ llvm/lib/Target/Alpha/Alpha.td Wed Jan 24 15:09:16 2007 > @@ -22,8 +22,6 @@ > > def FeatureCIX : SubtargetFeature<"CIX", "HasCT", "true", > "Enable CIX extentions">; > -def FeatureFIX : SubtargetFeature<"FIX", "HasF2I", "true", > - "Enable FIX extentions">; > > > //===----------------------------------------------------------------------===// > // Register File Description > @@ -54,10 +52,8 @@ > > //===----------------------------------------------------------------------===// > > def : Processor<"generic", Alpha21264Itineraries, []>; > -def : Processor<"pca56" , Alpha21264Itineraries, []>; > -def : Processor<"ev56" , Alpha21264Itineraries, []>; > -def : Processor<"ev6" , Alpha21264Itineraries, [FeatureFIX]>; > -def : Processor<"ev67" , Alpha21264Itineraries, [FeatureFIX, FeatureCIX]>; > +def : Processor<"ev6" , Alpha21264Itineraries, []>; > +def : Processor<"ev67" , Alpha21264Itineraries, [FeatureCIX]>; > > > //===----------------------------------------------------------------------===// > // The Alpha Target > > > Index: llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp > diff -u llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.61 > llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.62 > --- llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp:1.61 Wed Jan 24 01:03:39 > 2007 > +++ llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp Wed Jan 24 15:09:16 2007 > @@ -190,11 +190,10 @@ > bool AlphaAsmPrinter::doInitialization(Module &M) > { > AsmPrinter::doInitialization(M); > - if(TM.getSubtarget<AlphaSubtarget>().hasF2I() > - || TM.getSubtarget<AlphaSubtarget>().hasCT()) > - O << "\t.arch ev6\n"; > + if(TM.getSubtarget<AlphaSubtarget>().hasCT()) > + O << "\t.arch ev6\n"; //This might need to be ev67, so leave this test > here > else > - O << "\t.arch ev56\n"; > + O << "\t.arch ev6\n"; > O << "\t.set noat\n"; > return false; > } > > > Index: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp > diff -u llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.67 > llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.68 > --- llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.67 Wed Jan 24 12:43:14 > 2007 > +++ llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp Wed Jan 24 15:09:16 2007 > @@ -394,24 +394,10 @@ > default: break; > } > > - SDOperand LD; > - if (AlphaLowering.hasITOF()) { > - LD = CurDAG->getNode(AlphaISD::FTOIT_, MVT::i64, SDOperand(cmp, 0)); > - } else { > - int FrameIdx = > - CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, > 8); > - SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64); > - SDOperand ST = > - SDOperand(CurDAG->getTargetNode(Alpha::STT, MVT::Other, > - SDOperand(cmp, 0), FI, > - CurDAG->getRegister(Alpha::R31, > MVT::i64)), 0); > - LD = SDOperand(CurDAG->getTargetNode(Alpha::LDQ, MVT::i64, FI, > - CurDAG->getRegister(Alpha::R31, > MVT::i64), > - ST), 0); > - } > + SDNode* LD = CurDAG->getTargetNode(Alpha::FTOIT, MVT::i64, > SDOperand(cmp, 0)); > return CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64, > CurDAG->getRegister(Alpha::R31, MVT::i64), > - LD); > + SDOperand(LD,0)); > } > break; > > @@ -424,7 +410,6 @@ > // so that things like this can be caught in fall though code > //move int to fp > bool isDouble = N->getValueType(0) == MVT::f64; > - SDOperand LD; > SDOperand cond = N->getOperand(0); > SDOperand TV = N->getOperand(1); > SDOperand FV = N->getOperand(2); > @@ -432,21 +417,9 @@ > AddToISelQueue(TV); > AddToISelQueue(FV); > > - if (AlphaLowering.hasITOF()) { > - LD = CurDAG->getNode(AlphaISD::ITOFT_, MVT::f64, cond); > - } else { > - int FrameIdx = > - CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, > 8); > - SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64); > - SDOperand ST = > - SDOperand(CurDAG->getTargetNode(Alpha::STQ, MVT::Other, > - cond, FI, > CurDAG->getRegister(Alpha::R31, MVT::i64)), 0); > - LD = SDOperand(CurDAG->getTargetNode(Alpha::LDT, MVT::f64, FI, > - CurDAG->getRegister(Alpha::R31, > MVT::i64), > - ST), 0); > - } > + SDNode* LD = CurDAG->getTargetNode(Alpha::ITOFT, MVT::f64, cond); > return CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES, > - MVT::f64, FV, TV, LD); > + MVT::f64, FV, TV, SDOperand(LD,0)); > } > break; > > > > Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp > diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.76 > llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.77 > --- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.76 Sat Dec 30 23:55:36 > 2006 > +++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp Wed Jan 24 15:09:16 2007 > @@ -104,6 +104,8 @@ > > setOperationAction(ISD::SETCC, MVT::f32, Promote); > > + setOperationAction(ISD::BIT_CONVERT, MVT::f32, Promote); > + > // We don't have line number support yet. > setOperationAction(ISD::LOCATION, MVT::Other, Expand); > setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); > @@ -143,15 +145,11 @@ > setJumpBufAlignment(16); > > computeRegisterProperties(); > - > - useITOF = TM.getSubtarget<AlphaSubtarget>().hasF2I(); > } > > const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const { > switch (Opcode) { > default: return 0; > - case AlphaISD::ITOFT_: return "Alpha::ITOFT_"; > - case AlphaISD::FTOIT_: return "Alpha::FTOIT_"; > case AlphaISD::CVTQT_: return "Alpha::CVTQT_"; > case AlphaISD::CVTQS_: return "Alpha::CVTQS_"; > case AlphaISD::CVTTQ_: return "Alpha::CVTTQ_"; > @@ -398,16 +396,7 @@ > "Unhandled SINT_TO_FP type in custom expander!"); > SDOperand LD; > bool isDouble = MVT::f64 == Op.getValueType(); > - if (useITOF) { > - LD = DAG.getNode(AlphaISD::ITOFT_, MVT::f64, Op.getOperand(0)); > - } else { > - int FrameIdx = > - DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8); > - SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64); > - SDOperand ST = DAG.getStore(DAG.getEntryNode(), > - Op.getOperand(0), FI, NULL, 0); > - LD = DAG.getLoad(MVT::f64, ST, FI, NULL, 0); > - } > + LD = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0)); > SDOperand FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_, > isDouble?MVT::f64:MVT::f32, LD); > return FP; > @@ -421,15 +410,7 @@ > > src = DAG.getNode(AlphaISD::CVTTQ_, MVT::f64, src); > > - if (useITOF) { > - return DAG.getNode(AlphaISD::FTOIT_, MVT::i64, src); > - } else { > - int FrameIdx = > - DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8); > - SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64); > - SDOperand ST = DAG.getStore(DAG.getEntryNode(), src, FI, NULL, 0); > - return DAG.getLoad(MVT::i64, ST, FI, NULL, 0); > - } > + return DAG.getNode(ISD::BIT_CONVERT, MVT::i64, src); > } > case ISD::ConstantPool: { > ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); > > > Index: llvm/lib/Target/Alpha/AlphaISelLowering.h > diff -u llvm/lib/Target/Alpha/AlphaISelLowering.h:1.23 > llvm/lib/Target/Alpha/AlphaISelLowering.h:1.24 > --- llvm/lib/Target/Alpha/AlphaISelLowering.h:1.23 Sat Dec 30 23:55:36 > 2006 > +++ llvm/lib/Target/Alpha/AlphaISelLowering.h Wed Jan 24 15:09:16 2007 > @@ -27,7 +27,7 @@ > // Start the numbering where the builting ops and target ops leave off. > FIRST_NUMBER = ISD::BUILTIN_OP_END+Alpha::INSTRUCTION_LIST_END, > //These corrospond to the identical Instruction > - ITOFT_, FTOIT_, CVTQT_, CVTQS_, CVTTQ_, > + CVTQT_, CVTQS_, CVTTQ_, > > /// GPRelHi/GPRelLo - These represent the high and low 16-bit > /// parts of a global address respectively. > > > Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td > diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.136 > llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.137 > --- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.136 Thu Dec 7 11:39:14 > 2006 > +++ llvm/lib/Target/Alpha/AlphaInstrInfo.td Wed Jan 24 15:09:16 2007 > @@ -19,8 +19,6 @@ > def SDTFPUnaryOpUnC : SDTypeProfile<1, 1, [ > SDTCisFP<1>, SDTCisFP<0> > ]>; > -def Alpha_itoft : SDNode<"AlphaISD::ITOFT_", SDTIntToFPOp, []>; > -def Alpha_ftoit : SDNode<"AlphaISD::FTOIT_", SDTFPToIntOp, []>; > def Alpha_cvtqt : SDNode<"AlphaISD::CVTQT_", SDTFPUnaryOpUnC, []>; > def Alpha_cvtqs : SDNode<"AlphaISD::CVTQS_", SDTFPUnaryOpUnC, []>; > def Alpha_cvttq : SDNode<"AlphaISD::CVTTQ_" , SDTFPUnaryOp, []>; > @@ -745,12 +743,12 @@ > def FTOIS : FPForm<0x1C, 0x078, "ftois $RA,$RC",[], s_ftoi>; //Floating to > integer move, S_floating > let OperandList = (ops GPRC:$RC, F8RC:$RA), Fb = 31 in > def FTOIT : FPForm<0x1C, 0x070, "ftoit $RA,$RC", > - [(set GPRC:$RC, (Alpha_ftoit F8RC:$RA))], s_ftoi>; //Floating to > integer move > + [(set GPRC:$RC, (bitconvert F8RC:$RA))], s_ftoi>; //Floating to > integer move > let OperandList = (ops F4RC:$RC, GPRC:$RA), Fb = 31 in > def ITOFS : FPForm<0x14, 0x004, "itofs $RA,$RC",[], s_itof>; //Integer to > floating move, S_floating > let OperandList = (ops F8RC:$RC, GPRC:$RA), Fb = 31 in > def ITOFT : FPForm<0x14, 0x024, "itoft $RA,$RC", > - [(set F8RC:$RC, (Alpha_itoft GPRC:$RA))], s_itof>; //Integer to > floating move > + [(set F8RC:$RC, (bitconvert GPRC:$RA))], s_itof>; //Integer to > floating move > > > let OperandList = (ops F4RC:$RC, F8RC:$RB), Fa = 31 in > > > Index: llvm/lib/Target/Alpha/AlphaSubtarget.cpp > diff -u llvm/lib/Target/Alpha/AlphaSubtarget.cpp:1.7 > llvm/lib/Target/Alpha/AlphaSubtarget.cpp:1.8 > --- llvm/lib/Target/Alpha/AlphaSubtarget.cpp:1.7 Wed Oct 26 12:30:34 > 2005 > +++ llvm/lib/Target/Alpha/AlphaSubtarget.cpp Wed Jan 24 15:09:16 2007 > @@ -17,7 +17,7 @@ > using namespace llvm; > > AlphaSubtarget::AlphaSubtarget(const Module &M, const std::string &FS) > - : HasF2I(false), HasCT(false) { > + : HasCT(false) { > std::string CPU = "generic"; > > // Parse features string. > > > Index: llvm/lib/Target/Alpha/AlphaSubtarget.h > diff -u llvm/lib/Target/Alpha/AlphaSubtarget.h:1.5 > llvm/lib/Target/Alpha/AlphaSubtarget.h:1.6 > --- llvm/lib/Target/Alpha/AlphaSubtarget.h:1.5 Thu Mar 9 11:16:45 2006 > +++ llvm/lib/Target/Alpha/AlphaSubtarget.h Wed Jan 24 15:09:16 2007 > @@ -25,8 +25,6 @@ > class AlphaSubtarget : public TargetSubtarget { > protected: > > - /// Used by the ISel to turn in optimizations for POWER4-derived > architectures > - bool HasF2I; > bool HasCT; > > InstrItineraryData InstrItins; > @@ -41,7 +39,6 @@ > /// subtarget options. Definition of function is auto generated by tblgen. > void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU); > > - bool hasF2I() const { return HasF2I; } > bool hasCT() const { return HasCT; } > }; > } // End llvm namespace > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits@cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits