Changes in directory llvm/lib/Target/ARM:
ARMISelLowering.cpp updated: 1.8 -> 1.9 --- Log message: Observe -soft-float. --- Diffs of the changes: (+4 -3) ARMISelLowering.cpp | 7 ++++--- 1 files changed, 4 insertions(+), 3 deletions(-) Index: llvm/lib/Target/ARM/ARMISelLowering.cpp diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.8 llvm/lib/Target/ARM/ARMISelLowering.cpp:1.9 --- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.8 Tue Jan 30 14:37:08 2007 +++ llvm/lib/Target/ARM/ARMISelLowering.cpp Wed Jan 31 02:40:13 2007 @@ -28,6 +28,7 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/SSARegMap.h" +#include "llvm/Target/TargetOptions.h" #include "llvm/ADT/VectorExtras.h" using namespace llvm; @@ -36,7 +37,7 @@ Subtarget = &TM.getSubtarget<ARMSubtarget>(); // Uses VFP for Thumb libfuncs if available. - if (Subtarget->isThumb() && Subtarget->hasVFP2()) { + if (!UseSoftFloat && Subtarget->isThumb() && Subtarget->hasVFP2()) { // Single-precision floating-point arithmetic. setLibcallName(RTLIB::ADD_F32, "__addsf3vfp"); setLibcallName(RTLIB::SUB_F32, "__subsf3vfp"); @@ -91,7 +92,7 @@ } addRegisterClass(MVT::i32, ARM::GPRRegisterClass); - if (Subtarget->hasVFP2() && !Subtarget->isThumb()) { + if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) { addRegisterClass(MVT::f32, ARM::SPRRegisterClass); addRegisterClass(MVT::f64, ARM::DPRRegisterClass); } @@ -173,7 +174,7 @@ } setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); - if (Subtarget->hasVFP2() && !Subtarget->isThumb()) + if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) // Turn f64->i64 into FMRRD iff target supports vfp2. setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom); _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits