Changes in directory llvm/lib/Target/X86:
X86RegisterInfo.cpp updated: 1.200 -> 1.201 X86RegisterInfo.h updated: 1.45 -> 1.46 --- Log message: Added getReservedRegs(). --- Diffs of the changes: (+22 -0) X86RegisterInfo.cpp | 16 ++++++++++++++++ X86RegisterInfo.h | 6 ++++++ 2 files changed, 22 insertions(+) Index: llvm/lib/Target/X86/X86RegisterInfo.cpp diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.200 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.201 --- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.200 Mon Jan 29 17:20:22 2007 +++ llvm/lib/Target/X86/X86RegisterInfo.cpp Sat Feb 17 05:06:00 2007 @@ -31,6 +31,7 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Support/CommandLine.h" +#include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" using namespace llvm; @@ -883,6 +884,21 @@ return Is64Bit ? CalleeSavedRegClasses64Bit : CalleeSavedRegClasses32Bit; } +BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const { + BitVector Reserved(getNumRegs()); + Reserved.set(X86::RSP); + Reserved.set(X86::ESP); + Reserved.set(X86::SP); + Reserved.set(X86::SPL); + if (hasFP(MF)) { + Reserved.set(X86::RBP); + Reserved.set(X86::EBP); + Reserved.set(X86::BP); + Reserved.set(X86::BPL); + } + return Reserved; +} + //===----------------------------------------------------------------------===// // Stack Frame Processing methods //===----------------------------------------------------------------------===// Index: llvm/lib/Target/X86/X86RegisterInfo.h diff -u llvm/lib/Target/X86/X86RegisterInfo.h:1.45 llvm/lib/Target/X86/X86RegisterInfo.h:1.46 --- llvm/lib/Target/X86/X86RegisterInfo.h:1.45 Wed Jan 24 13:15:24 2007 +++ llvm/lib/Target/X86/X86RegisterInfo.h Sat Feb 17 05:06:00 2007 @@ -78,6 +78,12 @@ /// length of this list match the getCalleeSavedRegs() list. const TargetRegisterClass* const* getCalleeSavedRegClasses() const; + /// getReservedRegs - Returns a bitset indexed by physical register number + /// indicating if a register is a special register that has particular uses and + /// should be considered unavailable at all times, e.g. SP, RA. This is used by + /// register scavenger to determine what registers are free. + BitVector getReservedRegs(const MachineFunction &MF) const; + bool hasFP(const MachineFunction &MF) const; void eliminateCallFramePseudoInstr(MachineFunction &MF, _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits