[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAGISel.cpp updated: 1.392 -> 1.393
---
Log message:

Implement support for vector operands to inline asm, implementing
CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll


---
Diffs of the changes:  (+16 -4)

 SelectionDAGISel.cpp |   20 ++++++++++++++++----
 1 files changed, 16 insertions(+), 4 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.392 
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.393
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.392    Sat Mar 24 
21:14:49 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp  Sun Mar 25 00:00:54 2007
@@ -2387,14 +2387,23 @@
   if (RegVT == ValueVT)
     return Val;
   
+  if (MVT::isVector(RegVT)) {
+    assert(ValueVT == MVT::Vector && "Unknown vector conversion!");
+    return DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Val, 
+                       DAG.getConstant(MVT::getVectorNumElements(RegVT),
+                                       MVT::i32),
+                       DAG.getValueType(MVT::getVectorBaseType(RegVT)));
+  }
+  
   if (MVT::isInteger(RegVT)) {
     if (ValueVT < RegVT)
       return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
     else
       return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
-  } else {
-    return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
   }
+  
+  assert(MVT::isFloatingPoint(RegVT) && MVT::isFloatingPoint(ValueVT));
+  return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
 }
 
 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
@@ -2407,7 +2416,10 @@
     // If there is a single register and the types differ, this must be
     // a promotion.
     if (RegVT != ValueVT) {
-      if (MVT::isInteger(RegVT)) {
+      if (MVT::isVector(RegVT)) {
+        assert(Val.getValueType() == MVT::Vector &&"Not a vector-vector 
cast?");
+        Val = DAG.getNode(ISD::VBIT_CONVERT, RegVT, Val);
+      } else if (MVT::isInteger(RegVT)) {
         if (RegVT < ValueVT)
           Val = DAG.getNode(ISD::TRUNCATE, RegVT, Val);
         else
@@ -3424,7 +3436,7 @@
       // If this value was promoted, truncate it down.
       if (ResVal.getValueType() != VT) {
         if (VT == MVT::Vector) {
-          // Insert a VBITCONVERT to convert from the packed result type to the
+          // Insert a VBIT_CONVERT to convert from the packed result type to 
the
           // MVT::Vector type.
           unsigned NumElems = cast<VectorType>(RetTy)->getNumElements();
           const Type *EltTy = cast<VectorType>(RetTy)->getElementType();



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