Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.416 -> 1.417
---
Log message:
the result of an inline asm copy can be an arbitrary VT that the register
class supports. In the case of vectors, this means we often get the wrong
type (e.g. we get v4f32 instead of v8i16). Make sure to convert the vector
result to the right type. This fixes
CodeGen/X86/2007-04-11-InlineAsmVectorResult.ll
---
Diffs of the changes: (+21 -4)
SelectionDAGISel.cpp | 25 +++++++++++++++++++++----
1 files changed, 21 insertions(+), 4 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.416
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.417
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.416 Wed Apr 11
21:48:46 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Apr 12 01:00:20 2007
@@ -3055,9 +3055,10 @@
// how to maintain the constraint. If it isn't, go ahead and create vreg
// and let the regalloc do the right thing.
if (!isOutReg || !isInReg) {
- if (VT == MVT::Other)
- ValueVT = *PhysReg.second->vt_begin();
RegVT = *PhysReg.second->vt_begin();
+
+ if (VT == MVT::Other)
+ ValueVT = RegVT;
// Create the appropriate number of virtual registers.
SSARegMap *RegMap = DAG.getMachineFunction().getSSARegMap();
@@ -3459,8 +3460,24 @@
// If this asm returns a register value, copy the result from that register
// and set it as the value of the call.
- if (!RetValRegs.Regs.empty())
- setValue(&I, RetValRegs.getCopyFromRegs(DAG, Chain, Flag));
+ if (!RetValRegs.Regs.empty()) {
+ SDOperand Val = RetValRegs.getCopyFromRegs(DAG, Chain, Flag);
+
+ // If the result of the inline asm is a vector, it may have the wrong
+ // width/num elts. Make sure to convert it to the right type with
+ // vbit_convert.
+ if (Val.getValueType() == MVT::Vector) {
+ const VectorType *VTy = cast<VectorType>(I.getType());
+ unsigned DesiredNumElts = VTy->getNumElements();
+ MVT::ValueType DesiredEltVT = TLI.getValueType(VTy->getElementType());
+
+ Val = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Val,
+ DAG.getConstant(DesiredNumElts, MVT::i32),
+ DAG.getValueType(DesiredEltVT));
+ }
+
+ setValue(&I, Val);
+ }
std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
_______________________________________________
llvm-commits mailing list
[EMAIL PROTECTED]
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
