On Jun 15, 2007, at 11:17 PM, Bill Wendling wrote: > Fix a failure to bit_convert from integer GPR to MMX register.
Bill, this causes a regression on this testcase: define double @test2(i64 %A) { %B = bitcast i64 %A to double ret double %B } $ llvm-as < t.ll | llc -march=x86-64 before: .align 4 .globl _test2 _test2: movd %rdi, %xmm0 ret after: _test2: subq $8, %rsp movq %rdi, (%rsp) movsd (%rsp), %xmm0 addq $8, %rsp ret Please fix or revert your patch until you can, -Chris > > --- > Diffs of the changes: (+2 -0) > > X86ISelLowering.cpp | 2 ++ > 1 files changed, 2 insertions(+) > > > Index: llvm/lib/Target/X86/X86ISelLowering.cpp > diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.409 llvm/lib/ > Target/X86/X86ISelLowering.cpp:1.410 > --- llvm/lib/Target/X86/X86ISelLowering.cpp:1.409 Thu Jun 14 > 17:58:02 2007 > +++ llvm/lib/Target/X86/X86ISelLowering.cpp Sat Jun 16 01:17:31 2007 > @@ -394,6 +394,8 @@ > setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom); > setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Custom); > setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom); > + > + setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand); > } > > if (Subtarget->hasSSE1()) { > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits@cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits