On Oct 19, 2007, at 1:31 AM, Duncan Sands wrote:
> Hi Chris,
>
>> +void DAGTypeLegalizer::
>> +ExpandResult_SIGN_EXTEND_INREG(SDNode *N, SDOperand &Lo,
>> SDOperand &Hi) {
>> + GetExpandedOp(N->getOperand(0), Lo, Hi);
>> +
>> + // sext_inreg the low part if needed.
>> + Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, Lo.getValueType(), Lo,
>> + N->getOperand(1));
>> +
>> + // The high part gets the sign extension from the lo-part.
>> This handles
>> + // things like sextinreg V:i64 from i8.
>> + Hi = DAG.getNode(ISD::SRA, Hi.getValueType(), Lo,
>> + DAG.getConstant(MVT::getSizeInBits
>> (Hi.getValueType())-1,
>> + TLI.getShiftAmountTy()));
>> +}
>
> doesn't this assume that the type being extended is smaller than or
> equal to
> the type of Lo?
Yes, I think so. I just brought it over unmodified from legalizedag.cpp
> For example, will this work for i64 from i63?
Probably not, who does that stuff? :)
Assuming an expansion from i64 to 2x i32, the code above will work
for sextinreg amounts between 1 and 32. For greater amounts, the top
part should get a sextinreg, and the bottom part should or togther
the top and bottom shifted parts, similar to a expanded shift.
-Chris
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