Author: lattner
Date: Fri Nov 16 00:04:17 2007
New Revision: 44188

URL: http://llvm.org/viewvc/llvm-project?rev=44188&view=rev
Log:
Fix PR1800 by correcting mistaken logic.

Added:
    llvm/trunk/test/Transforms/InstCombine/2007-11-15-CompareMiscomp.ll
Modified:
    llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp?rev=44188&r1=44187&r2=44188&view=diff

==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/InstructionCombining.cpp Fri Nov 16 
00:04:17 2007
@@ -3577,8 +3577,7 @@
           case ICmpInst::ICMP_SGT:
             switch (RHSCC) {
             default: assert(0 && "Unknown integer condition code!");
-            case ICmpInst::ICMP_EQ:         // (X s> 13 & X == 15) -> X s> 13
-              return ReplaceInstUsesWith(I, LHS);
+            case ICmpInst::ICMP_EQ:         // (X s> 13 & X == 15) -> X == 15
             case ICmpInst::ICMP_SGT:        // (X s> 13 & X s> 15) -> X s> 15
               return ReplaceInstUsesWith(I, RHS);
             case ICmpInst::ICMP_UGT:        // (X s> 13 & X u> 15) -> no change

Added: llvm/trunk/test/Transforms/InstCombine/2007-11-15-CompareMiscomp.ll
URL: 
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/2007-11-15-CompareMiscomp.ll?rev=44188&view=auto

==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/2007-11-15-CompareMiscomp.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/2007-11-15-CompareMiscomp.ll Fri Nov 
16 00:04:17 2007
@@ -0,0 +1,10 @@
+; RUN: llvm-as < %s | opt -instcombine | llvm-dis | grep {icmp eq i32 %In, 1}
+; PR1800
+
+define i1 @test(i32 %In) {
+       %c1 = icmp sgt i32 %In, -1
+       %c2 = icmp eq i32 %In, 1
+       %V = and i1 %c1, %c2
+       ret i1 %V
+}
+


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