Author: lattner
Date: Mon Nov 19 15:16:54 2007
New Revision: 44242

URL: http://llvm.org/viewvc/llvm-project?rev=44242&view=rev
Log:
Implement vector expand support for shuffle_vector.  This fixes PR1811.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=44242&r1=44241&r2=44242&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Nov 19 15:16:54 2007
@@ -6286,6 +6286,41 @@
                                        TLI.getPointerTy()));
     break;
   }
+  case ISD::VECTOR_SHUFFLE: {
+    // Build the low part.
+    SDOperand Mask = Node->getOperand(2);
+    SmallVector<SDOperand, 8> Ops;
+    MVT::ValueType PtrVT = TLI.getPointerTy();
+    
+    // Insert all of the elements from the input that are needed.  We use 
+    // buildvector of extractelement here because the input vectors will have
+    // to be legalized, so this makes the code simpler.
+    for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
+      unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
+      SDOperand InVec = Node->getOperand(0);
+      if (Idx >= NumElements) {
+        InVec = Node->getOperand(1);
+        Idx -= NumElements;
+      }
+      Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
+                                DAG.getConstant(Idx, PtrVT)));
+    }
+    Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
+    Ops.clear();
+    
+    for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
+      unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
+      SDOperand InVec = Node->getOperand(0);
+      if (Idx >= NumElements) {
+        InVec = Node->getOperand(1);
+        Idx -= NumElements;
+      }
+      Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
+                                DAG.getConstant(Idx, PtrVT)));
+    }
+    Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
+    break;
+  }
   case ISD::BUILD_VECTOR: {
     SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 
                                     Node->op_begin()+NewNumElts_Lo);


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