Author: lattner Date: Sun Jan 6 17:38:27 2008 New Revision: 45667 URL: http://llvm.org/viewvc/llvm-project?rev=45667&view=rev Log: rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.
Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h llvm/trunk/lib/CodeGen/BranchFolding.cpp llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrThumb.td llvm/trunk/lib/Target/ARM/ARMInstrVFP.td llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp llvm/trunk/lib/Target/Alpha/AlphaInstrFormats.td llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td llvm/trunk/lib/Target/IA64/IA64InstrInfo.td llvm/trunk/lib/Target/Mips/MipsInstrInfo.td llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.cpp llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td llvm/trunk/lib/Target/Target.td llvm/trunk/lib/Target/X86/X86InstrFPStack.td llvm/trunk/lib/Target/X86/X86InstrInfo.td llvm/trunk/lib/Target/X86/X86InstrMMX.td llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/lib/Target/X86/X86InstrX86-64.td llvm/trunk/utils/TableGen/CodeGenInstruction.cpp llvm/trunk/utils/TableGen/CodeGenInstruction.h llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=45667&r1=45666&r2=45667&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Sun Jan 6 17:38:27 2008 @@ -48,7 +48,11 @@ const unsigned M_RET_FLAG = 1 << 2; const unsigned M_BARRIER_FLAG = 1 << 3; const unsigned M_DELAY_SLOT_FLAG = 1 << 4; -const unsigned M_LOAD_FLAG = 1 << 5; + +/// M_SIMPLE_LOAD_FLAG - This flag is set for instructions that are simple loads +/// from memory. This should only be set on instructions that load a value from +/// memory and return it in their only virtual register definition. +const unsigned M_SIMPLE_LOAD_FLAG = 1 << 5; /// M_MAY_STORE_FLAG - This flag is set to any instruction that could possibly /// modify memory. Instructions with this flag set are not necessarily simple @@ -184,6 +188,17 @@ /// findTiedToSrcOperand - Returns the operand that is tied to the specified /// dest operand. Returns -1 if there isn't one. int findTiedToSrcOperand(unsigned OpNum) const; + + + /// isSimpleLoad - Return true for instructions that are simple loads from + /// memory. This should only be set on instructions that load a value from + /// memory and return it in their only virtual register definition. + /// Instructions that return a value loaded from memory and then modified in + /// some way should not return true for this. + bool isSimpleLoad() const { + return Flags & M_SIMPLE_LOAD_FLAG; + } + }; @@ -279,9 +294,6 @@ bool isCall(MachineOpCode Opcode) const { return get(Opcode).Flags & M_CALL_FLAG; } - bool isLoad(MachineOpCode Opcode) const { - return get(Opcode).Flags & M_LOAD_FLAG; - } /// mayStore - Return true if this instruction could possibly modify memory. /// Instructions with this flag set are not necessarily simple store Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchFolding.cpp?rev=45667&r1=45666&r2=45667&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/BranchFolding.cpp (original) +++ llvm/trunk/lib/CodeGen/BranchFolding.cpp Sun Jan 6 17:38:27 2008 @@ -353,7 +353,7 @@ const TargetInstrDescriptor &TID = TII->get(I->getOpcode()); if (TID.Flags & M_CALL_FLAG) Time += 10; - else if (TID.Flags & (M_LOAD_FLAG|M_MAY_STORE_FLAG)) + else if (TID.isSimpleLoad() || (TID.Flags & M_MAY_STORE_FLAG)) Time += 2; else ++Time; Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=45667&r1=45666&r2=45667&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Sun Jan 6 17:38:27 2008 @@ -618,7 +618,7 @@ const TargetInstrDescriptor *TID = MI->getInstrDescriptor(); if ((TID->Flags & M_IMPLICIT_DEF_FLAG) || tii_->isTriviallyReMaterializable(MI)) { - isLoad = TID->Flags & M_LOAD_FLAG; + isLoad = TID->isSimpleLoad(); return true; } @@ -1226,7 +1226,7 @@ int LdSlot = 0; bool isLoadSS = DefIsReMat && tii_->isLoadFromStackSlot(ReMatDefMI, LdSlot); bool isLoad = isLoadSS || - (DefIsReMat && (ReMatDefMI->getInstrDescriptor()->Flags & M_LOAD_FLAG)); + (DefIsReMat && (ReMatDefMI->getInstrDescriptor()->isSimpleLoad())); bool IsFirstRange = true; for (LiveInterval::Ranges::const_iterator I = li.ranges.begin(), E = li.ranges.end(); I != E; ++I) { @@ -1308,7 +1308,7 @@ int LdSlot = 0; bool isLoadSS = DefIsReMat && tii_->isLoadFromStackSlot(ReMatDefMI, LdSlot); bool isLoad = isLoadSS || - (DefIsReMat && (ReMatDefMI->getInstrDescriptor()->Flags & M_LOAD_FLAG)); + (DefIsReMat && ReMatDefMI->getInstrDescriptor()->isSimpleLoad()); rewriteInstructionsForSpills(li, TrySplit, I, ReMatOrigDefMI, ReMatDefMI, Slot, LdSlot, isLoad, isLoadSS, DefIsReMat, CanDelete, vrm, RegInfo, rc, ReMatIds, loopInfo, @@ -1423,8 +1423,7 @@ int LdSlot = 0; bool isLoadSS = tii_->isLoadFromStackSlot(ReMatDefMI, LdSlot); // If the rematerializable def is a load, also try to fold it. - if (isLoadSS || - (ReMatDefMI->getInstrDescriptor()->Flags & M_LOAD_FLAG)) + if (isLoadSS || ReMatDefMI->getInstrDescriptor()->isSimpleLoad()) Folded = tryFoldMemoryOperand(MI, vrm, ReMatDefMI, index, Ops, isLoadSS, LdSlot, VReg); } Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp?rev=45667&r1=45666&r2=45667&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp Sun Jan 6 17:38:27 2008 @@ -202,7 +202,7 @@ unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); const TargetInstrDescriptor *TID = MI->getInstrDescriptor(); unsigned NumOps = TID->numOperands; - bool isLoad = (TID->Flags & M_LOAD_FLAG) != 0; + bool isLoad = TID->isSimpleLoad(); const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0); const MachineOperand &Base = MI->getOperand(2); const MachineOperand &Offset = MI->getOperand(NumOps-3); Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=45667&r1=45666&r2=45667&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Sun Jan 6 17:38:27 2008 @@ -684,7 +684,7 @@ Pseudo, "$cp:\n\tadd$p $dst, pc, $a", [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>; -let isLoad = 1, AddedComplexity = 10 in { +let isSimpleLoad = 1, AddedComplexity = 10 in { def PICLD : AXI2<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), Pseudo, "${addr:label}:\n\tldr$p $dst, $addr", [(set GPR:$dst, (load addrmodepc:$addr))]>; @@ -738,7 +738,7 @@ // FIXME: remove when we have a way to marking a MI with these properties. // FIXME: $dst1 should be a def. But the extra ops must be in the end of the // operand list. -let isLoad = 1, isReturn = 1, isTerminator = 1 in +let isSimpleLoad = 1, isReturn = 1, isTerminator = 1 in def LDM_RET : AXI4<0x0, (outs), (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops), LdFrm, "ldm${p}${addr:submode} $addr, $dst1", @@ -802,7 +802,7 @@ // // Load -let isLoad = 1 in { +let isSimpleLoad = 1 in { def LDR : AI2<0x0, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm, "ldr", " $dst, $addr", [(set GPR:$dst, (load addrmode2:$addr))]>; @@ -875,7 +875,7 @@ def LDRSB_POST: AI3po<0xD, (outs GPR:$dst, GPR:$base_wb), (ins GPR:$base,am3offset:$offset), LdFrm, "ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>; -} // isLoad +} // isSimpleLoad // Store def STR : AI2<0x0, (outs), (ins GPR:$src, addrmode2:$addr), StFrm, @@ -939,7 +939,7 @@ // // FIXME: $dst1 should be a def. -let isLoad = 1 in +let isSimpleLoad = 1 in def LDM : AXI4<0x0, (outs), (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops), LdFrm, "ldm${p}${addr:submode} $addr, $dst1", Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=45667&r1=45666&r2=45667&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Sun Jan 6 17:38:27 2008 @@ -188,7 +188,7 @@ } // FIXME: remove when we have a way to marking a MI with these properties. -let isLoad = 1, isReturn = 1, isTerminator = 1 in +let isSimpleLoad = 1, isReturn = 1, isTerminator = 1 in def tPOP_RET : TI<(outs reglist:$dst1, variable_ops), (ins), "pop $dst1", []>; @@ -237,7 +237,7 @@ // Load Store Instructions. // -let isLoad = 1 in { +let isSimpleLoad = 1 in { def tLDR : TI4<(outs GPR:$dst), (ins t_addrmode_s4:$addr), "ldr $dst, $addr", [(set GPR:$dst, (load t_addrmode_s4:$addr))]>; @@ -276,7 +276,7 @@ let isReMaterializable = 1 in def tLDRcp : TIs<(outs GPR:$dst), (ins i32imm:$addr), "ldr $dst, $addr", []>; -} // isLoad +} // isSimpleLoad def tSTR : TI4<(outs), (ins GPR:$src, t_addrmode_s4:$addr), "str $src, $addr", @@ -307,7 +307,7 @@ // TODO: A7-44: LDMIA - load multiple -let isLoad = 1 in +let isSimpleLoad = 1 in def tPOP : TI<(outs reglist:$dst1, variable_ops), (ins), "pop $dst1", []>; Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=45667&r1=45666&r2=45667&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Sun Jan 6 17:38:27 2008 @@ -88,7 +88,7 @@ // Load / store Instructions. // -let isLoad = 1 in { +let isSimpleLoad = 1 in { def FLDD : ADI5<(outs DPR:$dst), (ins addrmode5:$addr), "fldd", " $dst, $addr", [(set DPR:$dst, (load addrmode5:$addr))]>; @@ -96,7 +96,7 @@ def FLDS : ASI5<(outs SPR:$dst), (ins addrmode5:$addr), "flds", " $dst, $addr", [(set SPR:$dst, (load addrmode5:$addr))]>; -} // isLoad +} // isSimpleLoad def FSTD : ADI5<(outs), (ins DPR:$src, addrmode5:$addr), "fstd", " $src, $addr", @@ -110,7 +110,7 @@ // Load / store multiple Instructions. // -let isLoad = 1 in { +let isSimpleLoad = 1 in { def FLDMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dst1, variable_ops), "fldm${addr:submode}d${p} ${addr:base}, $dst1", @@ -120,7 +120,7 @@ variable_ops), "fldm${addr:submode}s${p} ${addr:base}, $dst1", []>; -} // isLoad +} // isSimpleLoad let mayStore = 1 in { def FSTMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$src1, Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp?rev=45667&r1=45666&r2=45667&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp Sun Jan 6 17:38:27 2008 @@ -690,7 +690,7 @@ } unsigned Opcode = MI.getOpcode(); - const TargetInstrDescriptor &Desc = TII.get(Opcode); + const TargetInstrDescriptor &Desc = *MI.getInstrDescriptor(); unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); bool isSub = false; @@ -885,7 +885,7 @@ assert(Offset && "This code isn't needed if offset already handled!"); if (isThumb) { - if (TII.isLoad(Opcode)) { + if (Desc.isSimpleLoad()) { // Use the destination register to materialize sp + offset. unsigned TmpReg = MI.getOperand(0).getReg(); bool UseRR = false; Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrFormats.td?rev=45667&r1=45666&r2=45667&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaInstrFormats.td (original) +++ llvm/trunk/lib/Target/Alpha/AlphaInstrFormats.td Sun Jan 6 17:38:27 2008 @@ -41,7 +41,7 @@ class MForm<bits<6> opcode, bit load, string asmstr, list<dag> pattern, InstrItinClass itin> : InstAlpha<opcode, asmstr, itin> { let Pattern = pattern; - let isLoad = load; + let isSimpleLoad = load; let Defs = [R28]; //We may use this for frame index calculations, so reserve it here bits<5> Ra; Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td?rev=45667&r1=45666&r2=45667&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td (original) +++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.td Sun Jan 6 17:38:27 2008 @@ -152,7 +152,7 @@ def WTF : PseudoInstAlpha<(outs), (ins variable_ops), "#wtf", [], s_pseudo>; -let isLoad = 1, hasCtrlDep = 1, Defs = [R30], Uses = [R30] in { +let hasCtrlDep = 1, Defs = [R30], Uses = [R30] in { def ADJUSTSTACKUP : PseudoInstAlpha<(outs), (ins s64imm:$amt), "; ADJUP $amt", [(callseq_start imm:$amt)], s_pseudo>; Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td?rev=45667&r1=45666&r2=45667&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td (original) +++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td Sun Jan 6 17:38:27 2008 @@ -47,7 +47,7 @@ // finally the X-form with the register-register. //===----------------------------------------------------------------------===// -let isLoad = 1 in { +let isSimpleLoad = 1 in { def LQDv16i8: RI10Form<0b00101100, (outs VECREG:$rT), (ins memri10:$src), "lqd\t$rT, $src", LoadStore, Modified: llvm/trunk/lib/Target/IA64/IA64InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/IA64/IA64InstrInfo.td?rev=45667&r1=45666&r2=45667&view=diff ============================================================================== --- llvm/trunk/lib/Target/IA64/IA64InstrInfo.td (original) +++ llvm/trunk/lib/Target/IA64/IA64InstrInfo.td Sun Jan 6 17:38:27 2008 @@ -558,7 +558,7 @@ "stf.spill [$dstPtr] = $value">, isM; } -let isLoad = 1 in { +let isSimpleLoad = 1 in { def LD1 : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$srcPtr), "ld1 $dst = [$srcPtr]">, isM; def LD2 : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$srcPtr), Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=45667&r1=45666&r2=45667&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Sun Jan 6 17:38:27 2008 @@ -205,7 +205,7 @@ [], IIAlu>; // Memory Load/Store -let isLoad = 1, hasDelaySlot = 1 in +let isSimpleLoad = 1, hasDelaySlot = 1 in class LoadM<bits<6> op, string instr_asm, PatFrag OpNode>: FI< op, (outs CPURegs:$dst), Modified: llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.cpp?rev=45667&r1=45666&r2=45667&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.cpp Sun Jan 6 17:38:27 2008 @@ -72,7 +72,7 @@ const TargetInstrDescriptor &TID = TII.get(Opcode); - isLoad = TID.Flags & M_LOAD_FLAG; + isLoad = TID.isSimpleLoad(); isStore = TID.Flags & M_MAY_STORE_FLAG; unsigned TSFlags = TID.TSFlags; Modified: llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td?rev=45667&r1=45666&r2=45667&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td Sun Jan 6 17:38:27 2008 @@ -365,7 +365,7 @@ // Sign extending loads. -let isLoad = 1, PPC970_Unit = 2 in { +let isSimpleLoad = 1, PPC970_Unit = 2 in { def LHA8: DForm_1<42, (outs G8RC:$rD), (ins memri:$src), "lha $rD, $src", LdStLHA, [(set G8RC:$rD, (sextloadi16 iaddr:$src))]>, @@ -394,7 +394,7 @@ } // Zero extending loads. -let isLoad = 1, PPC970_Unit = 2 in { +let isSimpleLoad = 1, PPC970_Unit = 2 in { def LBZ8 : DForm_1<34, (outs G8RC:$rD), (ins memri:$src), "lbz $rD, $src", LdStGeneral, [(set G8RC:$rD, (zextloadi8 iaddr:$src))]>; @@ -433,7 +433,7 @@ // Full 8-byte loads. -let isLoad = 1, PPC970_Unit = 2 in { +let isSimpleLoad = 1, PPC970_Unit = 2 in { def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src), "ld $rD, $src", LdStLD, [(set G8RC:$rD, (load ixaddr:$src))]>, isPPC64; Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td?rev=45667&r1=45666&r2=45667&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td Sun Jan 6 17:38:27 2008 @@ -202,7 +202,7 @@ "mtvscr $vB", LdStGeneral, [(int_ppc_altivec_mtvscr VRRC:$vB)]>; -let isLoad = 1, PPC970_Unit = 2 in { // Loads. +let isSimpleLoad = 1, PPC970_Unit = 2 in { // Loads. def LVEBX: XForm_1<31, 7, (outs VRRC:$vD), (ins memrr:$src), "lvebx $vD, $src", LdStGeneral, [(set VRRC:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>; Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=45667&r1=45666&r2=45667&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Sun Jan 6 17:38:27 2008 @@ -474,7 +474,7 @@ // // Unindexed (r+i) Loads. -let isLoad = 1, PPC970_Unit = 2 in { +let isSimpleLoad = 1, PPC970_Unit = 2 in { def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src), "lbz $rD, $src", LdStGeneral, [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>; @@ -531,7 +531,7 @@ // Indexed (r+r) Loads. // -let isLoad = 1, PPC970_Unit = 2 in { +let isSimpleLoad = 1, PPC970_Unit = 2 in { def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src), "lbzx $rD, $src", LdStGeneral, [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>; Modified: llvm/trunk/lib/Target/Target.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Target.td?rev=45667&r1=45666&r2=45667&view=diff ============================================================================== --- llvm/trunk/lib/Target/Target.td (original) +++ llvm/trunk/lib/Target/Target.td Sun Jan 6 17:38:27 2008 @@ -190,7 +190,7 @@ bit isIndirectBranch = 0; // Is this instruction an indirect branch? bit isBarrier = 0; // Can control flow fall through this instruction? bit isCall = 0; // Is this instruction a call instruction? - bit isLoad = 0; // Is this instruction a load instruction? + bit isSimpleLoad = 0; // Is this just a load instruction? bit mayStore = 0; // Can this instruction modify memory? bit isImplicitDef = 0; // Is this instruction an implicit def instruction? bit isTwoAddress = 0; // Is this a two address instruction? Modified: llvm/trunk/lib/Target/X86/X86InstrFPStack.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFPStack.td?rev=45667&r1=45666&r2=45667&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrFPStack.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrFPStack.td Sun Jan 6 17:38:27 2008 @@ -346,7 +346,7 @@ "fcmovnu\t{$op, %st(0)|%ST(0), $op}">, DB; // Floating point loads & stores. -let isLoad = 1 in { +let isSimpleLoad = 1 in { def LD_Fp32m : FpIf32<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP, [(set RFP32:$dst, (loadf32 addr:$src))]>; let isReMaterializable = 1, mayHaveSideEffects = 1 in Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=45667&r1=45666&r2=45667&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Sun Jan 6 17:38:27 2008 @@ -586,7 +586,7 @@ "mov{l}\t{$src, $dst|$dst, $src}", [(store (i32 imm:$src), addr:$dst)]>; -let isLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in { +let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in { def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src), "mov{b}\t{$src, $dst|$dst, $src}", [(set GR8:$dst, (load addr:$src))]>; @@ -2488,7 +2488,7 @@ "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize; def MOV32_rr : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32_:$src), "mov{l}\t{$src, $dst|$dst, $src}", []>; -let isLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in { +let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in { def MOV16_rm : I<0x8B, MRMSrcMem, (outs GR16_:$dst), (ins i16mem:$src), "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize; def MOV32_rm : I<0x8B, MRMSrcMem, (outs GR32_:$dst), (ins i32mem:$src), Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrMMX.td?rev=45667&r1=45666&r2=45667&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrMMX.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrMMX.td Sun Jan 6 17:38:27 2008 @@ -158,7 +158,7 @@ // Data Transfer Instructions def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src), "movd\t{$src, $dst|$dst, $src}", []>; -let isLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in +let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src), "movd\t{$src, $dst|$dst, $src}", []>; def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src), @@ -169,7 +169,7 @@ def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src), "movq\t{$src, $dst|$dst, $src}", []>; -let isLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in +let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src), "movq\t{$src, $dst|$dst, $src}", [(set VR64:$dst, (load_mmx addr:$src))]>; Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=45667&r1=45666&r2=45667&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Sun Jan 6 17:38:27 2008 @@ -301,7 +301,7 @@ // Move Instructions def MOVSSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src), "movss\t{$src, $dst|$dst, $src}", []>; -let isLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in +let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in def MOVSSrm : SSI<0x10, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src), "movss\t{$src, $dst|$dst, $src}", [(set FR32:$dst, (loadf32 addr:$src))]>; @@ -457,7 +457,7 @@ // Alias instruction to load FR32 from f128mem using movaps. Upper bits are // disregarded. -let isLoad = 1 in +let isSimpleLoad = 1 in def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src), "movaps\t{$src, $dst|$dst, $src}", [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>; @@ -634,7 +634,7 @@ // Move Instructions def MOVAPSrr : PSI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "movaps\t{$src, $dst|$dst, $src}", []>; -let isLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in +let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in def MOVAPSrm : PSI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), "movaps\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (alignedloadv4f32 addr:$src))]>; @@ -645,7 +645,7 @@ def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "movups\t{$src, $dst|$dst, $src}", []>; -let isLoad = 1 in +let isSimpleLoad = 1 in def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), "movups\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (loadv4f32 addr:$src))]>; @@ -654,7 +654,7 @@ [(store (v4f32 VR128:$src), addr:$dst)]>; // Intrinsic forms of MOVUPS load and store -let isLoad = 1 in +let isSimpleLoad = 1 in def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), "movups\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>; @@ -1003,7 +1003,7 @@ // Move Instructions def MOVSDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src), "movsd\t{$src, $dst|$dst, $src}", []>; -let isLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in +let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in def MOVSDrm : SDI<0x10, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src), "movsd\t{$src, $dst|$dst, $src}", [(set FR64:$dst, (loadf64 addr:$src))]>; @@ -1153,7 +1153,7 @@ // Alias instruction to load FR64 from f128mem using movapd. Upper bits are // disregarded. -let isLoad = 1 in +let isSimpleLoad = 1 in def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src), "movapd\t{$src, $dst|$dst, $src}", [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>; @@ -1330,7 +1330,7 @@ // Move Instructions def MOVAPDrr : PDI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "movapd\t{$src, $dst|$dst, $src}", []>; -let isLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in +let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in def MOVAPDrm : PDI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), "movapd\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (alignedloadv2f64 addr:$src))]>; @@ -1341,7 +1341,7 @@ def MOVUPDrr : PDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "movupd\t{$src, $dst|$dst, $src}", []>; -let isLoad = 1 in +let isSimpleLoad = 1 in def MOVUPDrm : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src), "movupd\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (loadv2f64 addr:$src))]>; @@ -1704,14 +1704,14 @@ // Move Instructions def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "movdqa\t{$src, $dst|$dst, $src}", []>; -let isLoad = 1 in +let isSimpleLoad = 1 in def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), "movdqa\t{$src, $dst|$dst, $src}", [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>; def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src), "movdqa\t{$src, $dst|$dst, $src}", [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>; -let isLoad = 1 in +let isSimpleLoad = 1 in def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), "movdqu\t{$src, $dst|$dst, $src}", [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>, @@ -1722,7 +1722,7 @@ XS, Requires<[HasSSE2]>; // Intrinsic forms of MOVDQU load and store -let isLoad = 1 in +let isSimpleLoad = 1 in def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), "movdqu\t{$src, $dst|$dst, $src}", [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>, Modified: llvm/trunk/lib/Target/X86/X86InstrX86-64.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrX86-64.td?rev=45667&r1=45666&r2=45667&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrX86-64.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrX86-64.td Sun Jan 6 17:38:27 2008 @@ -210,7 +210,7 @@ [(set GR64:$dst, i64immSExt32:$src)]>; } -let isLoad = 1 in +let isSimpleLoad = 1 in def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), "mov{q}\t{$src, $dst|$dst, $src}", [(set GR64:$dst, (load addr:$src))]>; Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.cpp?rev=45667&r1=45666&r2=45667&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenInstruction.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenInstruction.cpp Sun Jan 6 17:38:27 2008 @@ -84,7 +84,7 @@ isIndirectBranch = R->getValueAsBit("isIndirectBranch"); isBarrier = R->getValueAsBit("isBarrier"); isCall = R->getValueAsBit("isCall"); - isLoad = R->getValueAsBit("isLoad"); + isSimpleLoad = R->getValueAsBit("isSimpleLoad"); mayStore = R->getValueAsBit("mayStore"); isImplicitDef= R->getValueAsBit("isImplicitDef"); bool isTwoAddress = R->getValueAsBit("isTwoAddress"); Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.h?rev=45667&r1=45666&r2=45667&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenInstruction.h (original) +++ llvm/trunk/utils/TableGen/CodeGenInstruction.h Sun Jan 6 17:38:27 2008 @@ -94,7 +94,7 @@ bool isIndirectBranch; bool isBarrier; bool isCall; - bool isLoad; + bool isSimpleLoad; bool mayStore; bool isImplicitDef; bool isPredicable; Modified: llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp?rev=45667&r1=45666&r2=45667&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp Sun Jan 6 17:38:27 2008 @@ -210,7 +210,7 @@ } // These two override everything. - isLoad = Inst.isLoad; + isLoad = Inst.isSimpleLoad; NeverHasSideEffects = Inst.neverHasSideEffects; #if 0 @@ -308,7 +308,7 @@ if (Inst.isBarrier) OS << "|M_BARRIER_FLAG"; if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG"; if (Inst.isCall) OS << "|M_CALL_FLAG"; - if (isLoad) OS << "|M_LOAD_FLAG"; + if (isLoad) OS << "|M_SIMPLE_LOAD_FLAG"; if (mayStore) OS << "|M_MAY_STORE_FLAG"; if (Inst.isImplicitDef)OS << "|M_IMPLICIT_DEF_FLAG"; if (Inst.isPredicable) OS << "|M_PREDICABLE"; _______________________________________________ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits