[llvm-commits] [llvm] r47043 - in /llvm/trunk/lib: CodeGen/TargetInstrInfoImpl.cpp Target/PowerPC/PPCInstrInfo.cpp Target/X86/X86InstrInfo.cpp

[Evan Cheng]

Author: evancheng
Date: Tue Feb 12 20:46:49 2008
New Revision: 47043

URL: http://llvm.org/viewvc/llvm-project?rev=47043&view=rev
Log:
commuteInstr() can now commute non-ssa machine instrs.

Modified:
    llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp
    llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp

Modified: llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp?rev=47043&r1=47042&r2=47043&view=diff

==============================================================================
--- llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp Tue Feb 12 20:46:49 2008
@@ -23,8 +23,17 @@
          "This only knows how to commute register operands so far");
   unsigned Reg1 = MI->getOperand(1).getReg();
   unsigned Reg2 = MI->getOperand(2).getReg();
+  MachineOperand &MO = MI->getOperand(0);
+  bool UpdateReg0 = MO.isReg() && MO.getReg() == Reg1;
   bool Reg1IsKill = MI->getOperand(1).isKill();
   bool Reg2IsKill = MI->getOperand(2).isKill();
+  if (UpdateReg0) {
+    // Must be two address instruction!
+    assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
+           "Expecting a two-address instruction!");
+    Reg2IsKill = false;
+    MI->getOperand(0).setReg(Reg2);
+  }
   MI->getOperand(2).setReg(Reg1);
   MI->getOperand(1).setReg(Reg2);
   MI->getOperand(2).setIsKill(Reg1IsKill);

Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=47043&r1=47042&r2=47043&view=diff

==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Tue Feb 12 20:46:49 2008
@@ -147,10 +147,20 @@
   //   Op0 = (Op2 & ~M) | (Op1 & M)
 
   // Swap op1/op2
+  unsigned Reg0 = MI->getOperand(0).getReg();
   unsigned Reg1 = MI->getOperand(1).getReg();
   unsigned Reg2 = MI->getOperand(2).getReg();
   bool Reg1IsKill = MI->getOperand(1).isKill();
   bool Reg2IsKill = MI->getOperand(2).isKill();
+  // If machine instrs are no longer in two-address forms, update
+  // destination register as well.
+  if (Reg0 == Reg1) {
+    // Must be two address instruction!
+    assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
+           "Expecting a two-address instruction!");
+    MI->getOperand(0).setReg(Reg2);
+    Reg2IsKill = false;
+  }
   MI->getOperand(2).setReg(Reg1);
   MI->getOperand(1).setReg(Reg2);
   MI->getOperand(2).setIsKill(Reg1IsKill);

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: 
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=47043&r1=47042&r2=47043&view=diff

==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Tue Feb 12 20:46:49 2008
@@ -1055,6 +1055,15 @@
     unsigned C = MI->getOperand(2).getReg();
     bool BisKill = MI->getOperand(1).isKill();
     bool CisKill = MI->getOperand(2).isKill();
+    // If machine instrs are no longer in two-address forms, update
+    // destination register as well.
+    if (A == B) {
+      // Must be two address instruction!
+      assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
+             "Expecting a two-address instruction!");
+      A = C;
+      CisKill = false;
+    }
     return BuildMI(get(Opc), A).addReg(C, false, false, CisKill)
       .addReg(B, false, false, BisKill).addImm(Size-Amt);
   }


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