Hi Nate,
Nate Begeman wrote:
> Author: sampo
> Date: Tue Feb 12 20:58:33 2008
> New Revision: 47045
>
> URL: http://llvm.org/viewvc/llvm-project?rev=47045&view=rev
> Log:
> Make register scavenging happy by not using a reg (CR0) that isn't defined
>
>
I don't know about darwin, but this breaks linux/ppc32 JIT (llc works
fine). On a simple test case:
define i32 @main(i32 %argc) {
entry:
%tmp2 = add i32 2, %argc
ret i32 %tmp2
}
I get:
# Machine code for main():
Live Ins: r3 in VR#1024
Live Outs: r3
entry: 0x109cde80, LLVM BB @0x109c2640, ID#0:
Live Ins: %r3
%r3<def> = ADDI %r3<kill>, 2
BLR 20, %reg0, %r3<imp-use,kill>
# End machine code for main().
and the emission of the BLR instruction gives an error message:
Unhandled reg in PPCRegisterInfo::getRegisterNumbering!
It happens line 125 of PPCCodeEmitter.cpp. And the register number is zero.
Do you not get this on darwin?
Thanks,
Nicolas
> Modified:
> llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=47045&r1=47044&r2=47045&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Tue Feb 12 20:58:33 2008
> @@ -293,7 +293,7 @@
> // PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg
> // that doesn't matter.
> def pred : PredicateOperand<OtherVT, (ops imm, CRRC),
> - (ops (i32 20), CR0)> {
> + (ops (i32 20), (i32 zero_reg))> {
> let PrintMethod = "printPredicateOperand";
> }
>
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits@cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
_______________________________________________
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
