http://llvm.org/bugs/show_bug.cgi?id=18103
Bug ID: 18103
Summary: Double store/load instructions don't support optional
register arguments
Product: libraries
Version: trunk
Hardware: PC
OS: Linux
Status: NEW
Severity: normal
Priority: P
Component: Backend: ARM
Assignee: [email protected]
Reporter: [email protected]
CC: [email protected]
Classification: Unclassified
For example:
strexd r4, r0, [ip]
is rejected and needs to be written as
strexd r4, r0, r1, [ip]
Official ARM documents mark the r1 register as optional. It would be nice to
support this properly.
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