http://llvm.org/bugs/show_bug.cgi?id=20443
Bug ID: 20443
Summary: LLVM does not properly produce vectorized zextload
instructions
Product: libraries
Version: trunk
Hardware: PC
OS: Linux
Status: NEW
Severity: normal
Priority: P
Component: Backend: X86
Assignee: unassignedb...@nondot.org
Reporter: k...@google.com
CC: llvmbugs@cs.uiuc.edu
Classification: Unclassified
Created attachment 12823
--> http://llvm.org/bugs/attachment.cgi?id=12823&action=edit
Example .ll file deomonstrating problem with pmovzxbd
Hello,
I believe that LLVM is not producing the optimal machine code in the case of a
zextload command on vectorized types. The basic problem I have is that when I
have a pair of instructions like:
%6 = load <4 x i8>* %5, align 16
%7 = zext <4 x i8> %6 to <4 x i32>
LLVM produces the following assembly code:
pmovzxbd (%rdi), %xmm0
pand .LCPI0_0(%rip), %xmm0
The pand here is unnecessary since pmovzxbd already ensures that the zext has
been done. I have attached a file "sse_pmovzx_test.ll" that demonstrates this
issue.
In the scalar case things work just fine, so if the above .ll code used scalar
types, we would get a single assembly line of the form:
movzbl (%rdi), %eax
It seems like the vector SSE operations are not matching against the zextload
pattern, and it looks like this could be intentional. In DAGCombiner.cpp I
found this comment:
// fold (zext (load x)) -> (zext (truncate (zextload x)))
// None of the supported targets knows how to perform load and vector_zext
// on vectors in one instruction. We only perform this transformation on
// scalars.
if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
ISD::isUNINDEXEDLoad(N0.getNode()) &&
((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
So my question is what would it take to allow the combiner to make this
transformation for vector types? Is this comment out of date, since we now have
pmovzx** in SSE4.1 and vpmovzx** in AVX2?
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