http://llvm.org/bugs/show_bug.cgi?id=21313
Bug ID: 21313
Summary: [aarch64 disassembler] Some instructions do not have
correct condition flag set
Product: libraries
Version: 3.3
Hardware: All
OS: All
Status: NEW
Severity: normal
Priority: P
Component: Backend: AArch64
Assignee: [email protected]
Reporter: [email protected]
CC: [email protected]
Classification: Unclassified
Observed instructions are BL (marked as conditional) and CSNEG (marked as
unconditional).
This happens when after disassembling the opcode and getting the flags with
MCInstrInfo/MCInstrDesc:
const MCInstrDesc* MCID = &MCII->get(Inst.getOpcode());
if (MCID)
{
isCond = MCID->isConditionalBranch();
...
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