http://llvm.org/bugs/show_bug.cgi?id=22794
Bug ID: 22794
Summary: support AARCH32 cp15 register access by mrs/msr and
name
Product: clang
Version: 3.6
Hardware: PC
OS: Linux
Status: NEW
Severity: normal
Priority: P
Component: -New Bugs
Assignee: [email protected]
Reporter: [email protected]
CC: [email protected]
Classification: Unclassified
Support ARMv7/AARCH32 cp15 register access via mrs/msr and names instead of the
cryptic mrc/mcr would be nice. ARM has added support in ARMCC V5 added support
for it:
asm ("mrs %0, MPIDR" : "=r" (val));
so for Clang still this (cryptic) must be used:
asm ("mrc p15,0,%0,c0,c0,5;" : "=r" (val));
When targeting AARCH64 the names work nicely:
asm ("mrs %0, MPIDR_EL1"=r" (val));
At some point, native supporting this for 64-bit registers via a similar
mechnism would also be a nice thing. See
http://community.arm.com/groups/tools/blog/2014/10/16/msrrmrrs--a-asm-macro-for-64-bit-named-registers
So the cryptic
asm ("mrrc p15,0,%0,%1,c7":"=r"(val0),"=r"(val1));
can be used as this pseudo instruction:
asm ("mrrs %0,%1,PAR":"=r"(val0),"=r"(val1));
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