https://llvm.org/bugs/show_bug.cgi?id=23000
Bug ID: 23000
Summary: Immediates that need shifts are misassembled for ARM
Product: libraries
Version: trunk
Hardware: PC
OS: Linux
Status: NEW
Severity: normal
Priority: P
Component: Backend: ARM
Assignee: [email protected]
Reporter: [email protected]
CC: [email protected], [email protected],
[email protected], [email protected]
Classification: Unclassified
Try to assemble:
AES_Te:
.word 1,2,3,4,5,6
.word 1,2,3,4,5,6
.word 1,2,3,4,5,6
.word 1,2,3,4,5,6
.word 1,2,3,4,5,6
.word 1,2,3,4,5,6
.word 1,2,3,4,5,6
.word 1,2,3,4,5,6
.word 1,2,3,4,5,6
.word 1,2,3,4,5,6
.word 1,2,3,4,5,6
AES_encrypt:
sub r10,r3,#(AES_encrypt-AES_Te) @ Te
and disassemble. The immediate for the sub is misencoded. This is observed in
the OpenSSL assembly.
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