On Fri, Jun 15, 2012 at 05:31:14PM +0200, Lluís Batlle i Rossell wrote:
> I'm running vimprobable2 with webkit 1.4.0 in the fuloong (n32), and I get a
> SIGBUS
> (bad memory alignment I imagine).
>
> Has anyone experienced this and know a solution?
>
> Program received signal SIGBUS, Bus error.
> 0x7741334c in WebCore::TimerBase::stop() ()
> from
> /nix/store/lzp0jjhx3kcjh2wfkyca9fwv4cwpd4vp-webkit-1.4.0/lib/libwebkitgtk-1.0....
>
I've been researching this a bit. It's a misaligned access on SDC1. It's this
code:
=> 0x7741334c <+20>: b 0x77413010
<_ZN7WebCore9TimerBase15setNextFireTimeEd>
0x77413350 <+24>: sdc1 $f13,16(a0)
(gdb) info registers a0
a0: 0x730378dc
So, I think that a0 (the object base) is misaligned, as the 'cause' register
looks to indicate.
The C++ code:
class TimerBase {
...
virtual ~TimerBase();
double m_nextFireTime; // 0 if inactive
double m_repeatInterval; // 0 if not repeating
int m_heapIndex; // -1 if not in heap
unsigned m_heapInsertionOrder; // Used to keep order among equal-fire-time
timers
}
void TimerBase::stop()
{
m_repeatInterval = 0;
setNextFireTime(0);
}
The webkit (1.4.0) people use their own allocator for these objects; it says to
align to 8bytes, but it might be broken. More weirdly, the same member is
accessed in the TimerBase *constructor*, but nothing happened constructing.
Another alarming part, is *WHY SIGBUS*? The kernel should have traps for this.
But looking at arch/mips/kernel/unaligned.c:
case lwc1_op:
case ldc1_op:
case swc1_op:
case sdc1_op:
/*
* I herewith declare: this does not happen. So send SIGBUS.
*/
goto sigbus;
So if we implemented the kernel part, all solved! :)
Any volunteer? I don't know mips assembly right now.
Regards,
Lluís.
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