Lou Cypher wrote:
And the best I can have is an
"Optional dual buffer memories, 4K byte ping-pong,
for Tx and Rx"
So buffering at most *two* incoming packets.
Have to confess I never made a deep survey on silicon vendors' choices, at MAC
level, in the various devices (i.e. MCUs).
Taking the data sheet of an Ethernet enabled (integral MAC) MCU I see how their
buffering is "smarter", using some buffer descriptors, separating many variable
length packets in a FIFO.
If I return back to the FPGA ip-core, well, no signs of intelligent life, on
that planet (...)
The MAC you have for your FPGA is OK, only what you're missing is a DMA
engine. There are ip-core MACs including a DMA engine and there are
those not including it - you can still write your own DMA engine for the
MAC (especially if you need special handling in it). For a DMA-engine,
double-buffering is enough as long as the internal data bus is faster
DMA-ing received frames into RAM than receiving the next packet.
Of course, writing a DMA for the MAC is not done in a day, either...
Simon
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