Hello, Beware that everything should be cache line aligned! To be future proof assume cache size is 64 bytes, even if it's 32 bytes.
I recommend making the TX descriptors non-cacheable, bufferable and the RX descriptors non-cacheable, non-bufferable and the DMA buffers fully cacheable and use cache maintenance instructions before sending packets and after receiving them. Greetings, Indan _______________________________________________ lwip-users mailing list lwip-users@nongnu.org https://lists.nongnu.org/mailman/listinfo/lwip-users
