Hi Philip, It does work with both REX flavors, yes. Yes the keyboard is polled more frequently, but I have not seen a problem with that. Did you have something in mind?
On Sun, May 14, 2023 at 3:34 PM Philip Avery <pav...@xtra.co.nz> wrote: > Sounds great Steve. Will it work fine with Rex # & REXCPM? Also, the > keyboard would be accessed faster would it not? Does that cause a problem? > > Philip > > On 14/05/2023 1:51 am, Stephen Adolph wrote: > > I continue to hack away at making an easy to install clock doubler > > board for Model T computers. I realize that modifying hardware is not > > of interest to most, but I spend a lot of time on it myself. > > > > The point of the activity is to allow the user to switch from nominal > > 2.5MHz operation to 2x or 5MHz operation using a BASIC command. In > > M100/T102/NEC/M10/KC-85, all these variants have a very slow screen > > response time, and so doubling the clock rate makes the machine more > > responsive. Tandy 200 isn't as slow, but it is still nice to run fast. > > > > 5MHz operation is way outside of specifications, true. None of the > > parts in an M100 say they can run that fast. So far though, I have > > been making extensive use of it and have had no problems. The only > > issues that show up are when there is a timing loop in software that > > does not like being sped up. In situations like that, the user can > > downgrade to 2.5MHz mode. I think switchability is a must for this > > reason. > > > > So far I have successfully upgraded > > Model 100 (several! both older and newer) > > Tandy 102 (a few) > > Tandy 200 (one) > > > > Generally, when speeding up, the computer needs to run both the main > > ROM and the system RAM at 2x speed, and the power increases a bit. > > > > Main ROM speed: > > I have found that in the M100, for early production models, one needs > > to replace the main ROM for a faster one. Some later production use > > ROMs that are already fast enough. Tandy 102 and 200 ROMs seem fast > > enough. > > > > RAM speed: > > When the computer uses RAM that is 250nsec rated, these are often too > > slow. This can occur in M100, T102 and T200. In T200, I have no work > > around. The T200 needs 200nsec or faster RAM. In M100/T102, I have a > > work around that involves a simple cut/strap. > > > > Power: > > Consumption generally increases. For M100, with a nominal current of > > 56mA for the stock computer, a modified computer in 2.5MHz mode will > > see an increase to about 60mA. This is the "tax" paid for speed up > > capability. When operating in 5MHz mode, the current jumps to about > > 75mA or so. > > > > I'm attaching my current schematic for anyone interested in how the > > little board is designed. The board mounts on top of the 80C85, and > > steals the signals it needs directly from the CPU. There are 5 key > > circuits. > > > > 1) oscillator: generates 9.8304MHz > > > > 2) clock divider: generates 2.45MHz for the computer system > > components. Replaces the CLK output of the CPU, so that the > > downstream elements always run based on 2.45MHz. > > > > 3) State: a circuit that captures the user command to operate in > > either 1x or 2x clock speed. User command is OUT 85, 0 or OUT 85, 1. > > (80"85"). In T200, the real time clock RP5C01 is too slow for 5MHz > > operation, so the CL input is the chip select line for that part. The > > CL input forces the clock to 2.5MHz whenever the RC5C01 is accessed. > > > > 4) Clock select: This circuit uses 2 flip flops to generate either > > 9.8MHz or 4.9MHz depending on state. This circuit feeds clock to the > > 80C85. The original on-board crystal can be overdriven, no problem. > > > > 5) Astar signal: In M100/T102 (and likely M10 and 8201) the A* > > signal is used to gate the SRAM chip selects. What this signal does > > is it limits the "on" time of the SRAM, to limit power consumption. I > > was previously unaware of this trick. In 2x mode, the stock A* > > signal limits the access cycle time to the SRAM, and only fast SRAM > > (200nsec or less) can tolerate this. The solution for older machines > > with slower SRAM is to trigger A* earlier. This circuit generates > > "early A*" to resolve this problem. > > > > This implementation is now current and is being used in M100, T102 and > > T200. I'm planning to extend to M10 and NEC shortly, and if I > > encounter more changes I will update the design. > > > > My ultimate goal is to have a board that is as easy as possible to > > build and install, using SOIC parts (which I think are ok to hand > > solder) and through hole parts for the remainder. > > Currently the boar has 6 SOICs, 4 resistors, 4 caps and a crystal. > > > > The schematic is attached as a PNG for now, for the curious. > > > > Comments and questions welcome! > > If anyone is interested in the EAGLE board file, I'm happy to share it. > > > > Steve > > > >
