My guess would be that it has to do with the out-of-order scheduling in
the detailed CPU. If the instruction that reads curTick has no
dependence on the read or write instructions, then it will get executed
out-of-order while the read or write is still stalled.
I remember that we ran into this problem ourselves but I don't remember
the details of how we solved it... Ali or Nate, can you help here?
Steve
Richard R. Zhang wrote:
Hi Lisa and all M5 users,
I find something strange with the io access latency. Could you give me a hint
with it?
I have added a new instruction to the alpha isa. This instruction can get the
curTick in M5. It seems to work correctly. So, I plan to use it to measure the
time in the guest OS. Then, I added some statements to the ns83820 driver.
These statements compute the time used by the driver irq routine and the io
access(just compute the of writel and readl). But the results below puzzled me,
and I can't explain it. These results come from a netperf maerts test under
Sampler mode, and the memory configuration is STE.
-----------------------------------------------------------------------------
| | CacheCPU mode |
DetailedCPU mode |
-----------------------------------------------------------------------------
|avg.io read time | 1581 cycles |
40 cycles |
-----------------------------------------------------------------------------
|avg.io write time | 1561 cycles |
9 cycles |
-----------------------------------------------------------------------------
I don't know why the io access time in CacheCPU is much bigger than it in
DetailedCPU. I think that the time in CacheCPU mode should less than which in
DetailedCPU mode, at least equal to it. This is strange to me. Could anybody
give me the explain with it? Thanks a lot.
Best wishes,
Richard R. Zhang
2006-04-26
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