Hi Russ,
It shouldn't be too hard.. basically you'd have to duplicate the path that
read() takes from BaseDynInst through the CPU object (e.g., AlphaO3CPU) to
the o3 LSQ with prefetch() functions that will be similar. Once you get to
the LSQ then the key difference is to set the command field of the packet
you send to the dcache to SoftPFReq rather than ReadReq.
Maybe Kevin can speak up if there are subtleties I'm not aware of.
Let us know if it's not that simple...
Steve
On 7/12/07, Russ Joseph <[EMAIL PROTECTED]> wrote:
Hi,
It looks as if software prefetch instructions are ignored by the O3 model
in the m5 2.0 release (e.g. they 'execute' and 'commit' but do not impact
the microarchitectural state). In particular,
BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags) does nothing.
How difficult would it be to re-enable swp?
Thanks,
Russ
-------------------------------------------------------------
Russ Joseph Technological Institute
Assistant Professor 2145 Sheridan Road
Electrical Engineering and Evanston, IL 60208
Computer Science
Northwestern University voice: 847-491-3061
[EMAIL PROTECTED] fax: 847-467-4144
http://www.ece.northwestern.edu/~rjoseph
-------------------------------------------------------------
_______________________________________________
m5-users mailing list
[email protected]
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
_______________________________________________
m5-users mailing list
[email protected]
http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
