Thanks Steve ! I figured that out with the traces. However just tell me, i dont see any writebacks to physical memory if data is updated in L2 in the traces when i use flags="Bus cache" on command line? I am simulating a uniprocessor with L1 and L2.
If there are write backs to physical memory and there is a multiprocesor system, are they broadcasted over system bus like the read requests? ---- Original message ---- >Date: Sat, 24 Nov 2007 15:43:06 -0800 >From: "Steve Reinhardt" <[EMAIL PROTECTED]> >Subject: Re: [m5-users] WriteReq & WriteReqNoAck|Writeback >To: "M5 users mailing list" <[email protected]> > >On Nov 24, 2007 2:12 PM, Shoaib Akram <[EMAIL PROTECTED]> wrote: >> 1. >> Whenever, the packet intersects the bus and the command is WriteReq, >> recvFunctional() is called which carries no latency with it. Why this is so? > >Can you provide a file and line number to clarify what you're talking >about? In general that helps a lot. > >> >> 2. >> Does the command WriteReqNoAck|Writeback means an L2 write miss and the >> packet is broadcasted so all caches can update their value for that address >> and ultimate write back to memory. > >Writeback is just that, a writeback. > >Steve > >> _______________________________________________ >> m5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/m5-users >> >_______________________________________________ >m5-users mailing list >[email protected] >http://m5sim.org/cgi-bin/mailman/listinfo/m5-users _______________________________________________ m5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/m5-users
