> Am 18.08.2016 um 22:03 schrieb Ryan Carlyle <[email protected]>:
> 
> I don't know if this is directly relevant to MachineKit at all, but it's an 
> interesting read on how non-RT Linux handles GPIO under the hood on the BBB. 
> http://www.righto.com/2016/08/the-beaglebones-io-pins-inside-software.html

interesting article!

the BB and Rpi HAL GPIO driver do it more like in [3] under 'Notes and 
references'

that said - both the method suggested there, and the machinekit BB and Rpi 
drivers do it wrong, as do most of the 'fast GPIO' examples you find online

the problems are:
- use of /dev/mem - not a great idea, very easy to bring down the house with a 
stray pointer
- no protection against HAL and the stock GPIO driver fighting for the same 
resources, through bypassing device tree

I did not know better back then, but after learning how the FPGA folk do this 
(thanks to Michael Brown's stellar work) I would do it like so:

- create device tree overlays referencing the gpio hardware, exposing just the 
minimally needed regions
- make that overlay also refer to the uio driver which helps to mmap()'d device 
memory safely and minimally, not the whole memory space like through /dev/mem
- when loading the HAL driver, pass the overlay name as argument and have the 
HAL driver insert/remove the overlay, which will cause uio to expose the 
minimally necessary memory region
- the overlay scheme should also protect against multiple drivers claiming the 
same resource (I think)
- it might even be possible this scheme works for a non-root process - 
/dev/uio* permissions could be set via udev rules (actually we should try that, 
because if that works that would open the route to a non-root RTAPI demon).


a pretty good example of how that should look is the hm2_soc_ol.c driver for 
the Altera CycloneV and Xilinx Zynq platforms - that is about as 
'environmentally compatible' as I currently understand things: 
https://github.com/machinekit/machinekit/blob/master/src/hal/drivers/mesa-hostmot2/hm2_soc_ol.c
 (in this case, the device tree overlay not only exposes the FPGA memory region 
but also loads the FPGA bitfile)


- Michael


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