Hi Paul, We have just commited a bunch of bug fixes on the master branch. This issue did came up when we were testing the simulator and it was fixed in one of the patches, I dont remember exactly which one though.
This issue comes up because when a bus try to broadcast, it first checks entry available flag of all the controllers connected to that bus and then decides if it can broadcast or not. This check is done by calling 'can_broadcast' function in mesiBus.cpp. So once this check return success, the broadcast should be received by all the controllers as an atomic operation. So we assert when one of the controller is not able to make a local queue entry while bus is broadcasting, as it will break the atomic model of bus. Let me know if you still have issues with the latest bug fixes. - Avadh On Mon, Mar 29, 2010 at 6:44 PM, DRAM Ninjas <[email protected]> wrote: > Hello again, > > Currently I'm attempting to replace the memory system in MARSS with our own > models, and I'm running into a problem with an assertion failure when the > memory controller becomes full (i.e. when > MemoryController::handle_interconnect_cb() returns false which in turn fails > the assertion on mesiBus.cpp:315). This assertion seems to imply that the > memory controller should never be full. I was just wondering if it is > expected that a memory controller will never fill up or is this just an > assert that indicates that correct handling of a full memory controller is > future work? > > Thanks, > Paul > > > _______________________________________________ > http://www.marss86.org > Marss86-Devel mailing list > [email protected] > https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel > >
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