Greetings All, I am in the process of trying to tweak the cache hierarchy and I just had a few question since I believe the comments in cacheConstants.h don't match the actual code.
So let's say I want a 32kb L1D, 8 way set associative, 64 byte lines (I believe these are actual core 2 duo numbers for certain models). So the "way count" is the associativity, right? So I want WAY_COUNT=8, LINE_SIZE=64, SET_COUNT=64 = 64 * 8 * 64 = 32k. Are those the correct parameters? The other thing I haven't heard of before is L1D_DCACHE_BANKS ... what does this parameter do? It seems like it is also factored into the total size of the L1D, but the comment says that the cache should be 32KB with LINE_SIZE=16, SET_COUNT=2048, WAY_COUNT=2, BANKS=8 ... which doesn't seem right. Is this a case of just forgetting to update the comment? If the comment is incorrect, given these parameters, what is the size of the L1D? As far as cache statistics are concerned: is there a way to get only userland L2 cache misses? I'm running a workload where the L2 cache hit rate seems excessively high even though the workload is designed to be extremely cache unfriendly (though I must say I'm a bit overwhelmed at the ptlstats output and am not quite sure where to look). Using performance counters I'm getting on the order of 75% miss rate on my laptop. I'm wondering if there's maybe a discrepancy in how the L2 hit rate is computed. Is it simply (total L2 hits / total L2 references)? Thanks. Paul
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