On Wed, Nov 10, 2010 at 12:25 PM, Vidyabhushan Mohan <[email protected]>wrote:
> Hi. > I am Bhushan, a graduate student from University of Virginia. First of all, > I would like to let you know that I find marss(and ptlsim) very promising > and easy to understand. I have some questions regarding the usage of MARSS. > It would be great if someone has answers to them. > > *) I am trying to run MARSS with a 3-level cache hierarchy (private L1 - (I > and D) and L2 caches) and a shared L3 cache. For this, I defined > ENABLE_L3_CACHE in ptlsim/cache/memoryHierarchy.cpp and changed > cache_config_type to private_L2 in PTLsimConfig:reset() in > ptlsim/sim/ptlsim.cpp. > My question is - are these the only changes necessary to enable a 3 level > hierachy? Is there some way of checking (after qemu loads the OS) that the > system has infact been configured with 3-levels? Or if I compile in debug > mode, can I check for any debug outputs to determine if the cache is in > 2-level or 3-level? Also, is the cache configured as a 2-level hierarchy > (private L1 and shared L2) by default? > > One way to check if L3 is working correctly is to compile Marss in debug mode, and run it with loglevel set to 6 or more, then you'll see all the memory-hierarchy activities in the log file. Try to find memory log with L3 and you'll confirm if L3 is enabled or not. By default, L2 is configured as private cache. - Avadh > Thanks! > -- > Bhushan > > _______________________________________________ > http://www.marss86.org > Marss86-Devel mailing list > [email protected] > https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel > >
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