Hello, I have some general questions regarding MARSS.
I've been trying to find at the number of loads that failed to issue due to bank conflicts. Going through the code, I can see that PTLsim's memory implementation has been modified somewhat but some of the functions/statistics still remain in MARSS. For example, in ReorderBufferEntry:issueload(), 'dcache.load.issue.miss' is incremented whether or not there is a l1d hit or not. I'm curious as to which statistics are deprecated/unreliable in MARSS' current implementation. Is all of the /ooocore/dcache unreliable? Just as an aside, does the bank conflict code represent any real x86 implementation? I see that it compares the least significant number of bits of two addresses which issue on the same cycle; this would suggest that a cache line is divided and distributed amongst the banks. I was under the impression that most banked cache implementations will contain adjacent lines in different banks; this way the tag structure doesn't need to be multiported. It's simple to change the code to reflect this, I was just curious if the code in the current incarnation is reflective of something specific. :-) Kind regards Tim _______________________________________________ http://www.marss86.org Marss86-Devel mailing list [email protected] https://www.cs.binghamton.edu/mailman/listinfo/marss86-devel
